ADL5201

Data Sheet

Rev. 0 | Page 6 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO

A LOW IMPEDANCE GROUND PAD.

2

1

3

4

5

6

18

17

16

15

14

13

MODE0

MODE1

GND

VIN–

VIN+

GND

LATCH

VOUT+

VOUT–

VOUT+

VOUT–

VPOS

ADL5201

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4, EP

GND

Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.

2

VIN+

Positive Input.

3

VIN−

Negative Input.

5

MODE1

MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.

6

MODE0

LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.

7

SDIO/A5

Serial Data Input/Output (SDIO). When CS is pulled low, SDIO is used for reading and writing to the SPI port.

Bit 5 for Parallel Gain Control Interface (A5).

8

SCLK/A4

Serial Clock Input in SPI Mode (SCLK).

Bit 4 for Parallel Gain Control Interface (A4).

9

GS1/CS/A3

MSB for Gain Step Size Control in Up/Down Mode (GS1).

SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface.

Bit 3 for Parallel Gain Control Interface (A3).

10

GS0/FA/A2

LSB for Gain Step Size Control in Up/Down Mode (GS0).

Fast Attack (FA). In serial mode, a logic high (1.4 V ≤ FA ≤ 3.3 V) attenuates according to the FA setting in the SPI

word. Bit 2 for Parallel Gain Control Interface (A2).

11

UPDN_CLK/A1

Clock Interface for Up/Down Function (UPDN_CLK).

Bit 1 for Parallel Gain Control Interface (A1).

12

UPDN_DAT/A0

Data Pin for Up/Down Function (UPDN_DAT).

Bit 0 for Parallel Gain Control Interface (A0).

13

LATCH

A logic low (0 V ≤ LATCH ≤ 0.8 V) allows gain changes. A logic high (1.4 V ≤ LATCH ≤ 3.3 V) disallows gain

changes.

14, 16

VOUT+

Positive Output.

15, 17

VOUT−

Negative Output.

18, 21,

22, 23, 24

VPOS

Positive Power Supply.

19

PWUP

Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part.

20

PM

Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V)

enables low power mode.