ADL5201ACPZ-R7 datasheet(15/28 Pages) AD

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Data Sheet

ADL5201

Rev. 0 | Page 15 of 28

THEORY OF OPERATION

DIGITAL INTERFACE OVERVIEW

The ADL5201 DVGA has three digital gain control options:

parallel control interface, serial peripheral interface, and gain

up/down interface. The desired gain control option is selected via

two control pins, MODE0 and MODE1 (see Table 4 for the

truth table for the mode control pins). The gain code is in 6-bit

binary format. A voltage from 1.4 V to 3.3 V is required for a

logic high.

Two pins are common to all gain control options: PM and PWUP.

PM allows the user to choose operation in low power mode or

high performance mode. PWUP is the power-up pin. Physical

pins are shared among the three interfaces, resulting in as many

as three different functions per digital pin (see Table 3).

Table 4. Digital Control Interface Selection Truth Table

MODE1

MODE0

Interface

Parallel control

Serial peripheral (SPI)

Up/down

PARALLEL DIGITAL INTERFACE

The parallel digital interface uses six binary bits (Bits[A5:A0])

and a latch pin (LATCH). The Latch pin controls whether the

input data latch is transparent or latched. In transparent mode,

the gain changes as the input gain control bits change. In latched

mode, gain is determined by the latched gain setting and does

not change with the input gain control bits.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI uses three pins: SDIO, SCLK, and CS. The SPI data

ation step size address bits, one read/write bit, and seven don’t

care bits. SDIO is the serial data input and output pin. The

SCLK pin is the serial clock, and CS is the channel select pin.

DATA

READ/WRITE

DO NOT CARE

(7 BITS)

FAST ATTACK ATTENUATION

STEP SIZE ADDRESS

GAIN CONTROL

FA0

FA1

MSB LSB MSB

R/W DNC DNC DNC DNC DNC DNC DNC

Figure 49. 16-Bit SPI Register

To write to the SPI register, CS must be pulled low and 16 clock

pulses must be applied to SCLK. To read the SPI register value,

the R/W bit must be set high, CS must be pulled low, and the

part must be clocked. After the register is read out during the

next 16 clock cycles, the SPI is automatically placed in write mode.

Fast Attack

The fast attack feature, accessible via the SPI, allows the gain to

be reduced from its present gain setting by a predetermined step

size. Four different attenuation step sizes are available. The

truth table for fast attack is shown in Table 5.

Table 5. SPI 2-Bit Attenuation Step Size Truth Table

FA1

FA0

Step Size (dB)

SPI fast attack mode is controlled by the FA pin. A logic high

on the FA pin results in an attenuation that is selected by

Bits[FA1:FA0] in the SPI register.

UP/DOWN INTERFACE

The GS1 and GS0 pins control the up/down gain step function.

Gain is increased by a clock pulse on the UPDN_CLK pin

(rising and falling edges) when the UPDN_DAT pin is high.

Gain is decreased by a clock pulse on the UPDN_CLK pin

when the UPDN_DAT pin is low.

RESET

UPDN_DAT

UPDN_CLK

Figure 50. Up/Down Timing

Reset is detected by a rising edge latching data having one polarity,

with the falling edge latching the opposite polarity. Reset results

in a minimum binary gain code of 111111.

The truth table for the gain step function is shown in Table 6.

The step size is selectable using the GS1 and GS0 pins. The gain

is limited by the top and bottom of the control range.

Table 6. Gain Step Size Control Truth Table

GS1

GS0

Step Size (dB)

0.5

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