Data Sheet

ADL5201

Rev. 0 | Page 19 of 28

50Ω

AC

1:3

75Ω

75Ω

33Ω

33Ω

1µH

5V

1µH

5V

5V

0.1µF

0.1µF

0.1µF

47nH

47nH

0.1µF

DIGITAL

INTERFACE

ADL5201

14pF

AD9467

Figure 54. Wideband ADC Interfacing Example Featuring the ADL5201 and the AD9467

Figure 54 shows the ADL5201 driving a two-pole, 100 MHz, low-

pass filter into the AD9467. The AD9467 is a 16-bit, 200 MSPS

to 250 MSPS ADC with a buffered wideband input that presents

a 530 Ω differential input impedance and requires a 2 V or 2.5 V

input swing to reach full scale. For optimum performance, the

ADL5201 should be driven differentially, using an impedance

transformer or input balun.

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

0

20

40

60

80

100

120

140

160

180

200

FREQUENCY (MHz)

Figure 55. Measured Frequency Response of the Wideband

ADC Interface Shown in Figure 54

Figure 54 uses a 1:3 impedance transformer to provide the

150 Ω input impedance of the ADL5201 with a matched input.

The outputs of the ADL5201 are biased through the two 1 μH

inductors, and the two 0.1 μF capacitors on the outputs decouple

the 5 V inductor voltage from the input common-mode voltage

of the AD9467. The two 75 Ω resistors provide the 150 Ω load to

the ADL5201, whose gain is load dependent. The 47 nH induc-

tors and 14 pF capacitor constitute the (100 MHz − 1 dB) low-pass

filter. The two 33 Ω isolation resistors suppress any switching

currents from the ADC input sample-and-hold circuitry. The

circuit depicted in Figure 54 provides variable gain, isolation,

filtering, and source matching for the AD9467. By using this

circuit with the ADL5201 in a gain of 20 dB (maximum gain),

an SNR of 68 dB and an SFDR performance of 88 dBc are

achieved at 100 MHz, as shown in Figure 56.

0

–15

–30

–45

–60

–75

–90

–105

–120

–150

–135

0

15

30

45

60

75

90

105

120

FREQUENCY (MHz)

SNR = 68dB

SFDR = 88dBc

NOISE FLOOR = –114dBFS

FUND = –1.05dBFS

SECOND = –94.7dBc

THIRD = –88.75dBc

5

+

6

4

3

2

Figure 56. Measured Single-Tone Performance of the Circuit Shown

in Figure 54 for a 100 MHz Input Signal

The two-tone 100 MHz IMDs of two 1 V p-p signals have

an SFDR of greater than 91 dBc, as shown in Figure 57.

0

–15

–30

–45

–60

–75

–90

–105

–120

–150

–135

0

15

30

45

60

75

90

105

120

FREQUENCY (MHz)

FUND1 = –6.682dBFS

FUND2 = –7.096dBFS

2f1 – f2 = –93.2dBFS

2f2 – f1 = –92.58dBc

NOISE FLOOR = –115.3dBFS

f2 – f1

+

f1 + f2

2f2 + f1

2f1 – f2

2f2 – f1

2f1 + f2

Figure 57. Measured Two-Tone Performance of the

Circuit Shown in Figure 54 for a 100 MHz Input Signal