ADL5201ACPZ-R7 datasheet(16/28 Pages) AD

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ADL5201

Data Sheet

Rev. 0 | Page 16 of 28

Truth Table

Table 7. Gain Code vs. Voltage Gain Lookup Table

6-Bit Binary

Gain Code

Voltage

Gain (dB)

6-Bit Binary

Gain Code

Voltage

Gain (dB)

000000

100000

000001

19.5

100001

3.5

000010

100010

000011

18.5

100011

2.5

000100

100100

000101

17.5

100101

1.5

000110

100110

000111

16.5

100111

0.5

001000

101000

001001

15.5

101001

−0.5

001010

101010

−1

001011

14.5

101011

−1.5

001100

101100

−2

001101

13.5

101101

−2.5

001110

101110

−3

001111

12.5

101111

−3.5

010000

110000

−4

010001

11.5

110001

−4.5

010010

110010

−5

010011

10.5

110011

−5.5

010100

110100

−6

010101

9.5

110101

−6.5

010110

110110

−7

010111

8.5

110111

−7.5

011000

111000

−8

011001

7.5

111001

−8.5

011010

111010

−9

011011

6.5

111011

−9.5

011100

111100

−10

011101

5.5

111101

−10.5

011110

111110

−11

011111

4.5

111111

−11.5

LOGIC TIMING

To write to the ADL5201, refer to the timing shown in Figure 51.

The write mode uses a 16-bit serial word on the SDIO pin. The

R/W bit of the word must be low to write Bits[D5:D0], which are

the binary weighted codes for the attenuation level (0 = minimum

attenuation, 63 = maximum attenuation). The FA0 and FA1 bits

control the fast attack step size. The DNC bits are nonfunctional,

do not care bits.

Reading the ADL5201 SPI register requires the following two steps:

Set the R/W bit high using a 16-bit word and the timing

shown in Figure 51. All other bits are ignored when the

R/W bit is high.

The SDIO is used as an output during the next sequence.

The written pattern is serially clocked out on SDIO using

16 clocks and the timing shown in Figure 51. The R/W bit

automatically returns low to the write state following the

read sequence.

SCLK

SDIO

tSCLK

tDS

tDS tDH

tPW

tDH

DNC

R/W

FA1

FA0

Figure 51. SPI Interface Read/Write Mode Timing Diagram

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