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ADP1047ARQZ-R7 数据表(PDF) 79 Page - Analog Devices |
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ADP1047ARQZ-R7 数据表(HTML) 79 Page - Analog Devices |
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79 / 84 page ![]() Data Sheet ADP1047/ADP1048 Rev. 0 | Page 79 of 84 Table 148. Register 0xFE81—Latched Flag 1 Bits Bit Name R/W Description 7 RSVD R Reserved. 6 EEPROM_UNLOCKED R 1 = EEPROM is unlocked and its contents can be written. 5 EEPROM_CRC R 1 = downloaded EEPROM contents are incorrect. 4 I2C_ADDRESS R 1 = the resistor on the ADD pin has a value that can cause an error in the address assignment (the address falls too close to the threshold between two addresses). 3 LOW_LINE R 1 = input voltage is higher than the high line threshold. 2 FAST_OCP R 1 = the threshold set for the comparator on the ILIM pin has been crossed. 1 SYNC_LOCK R 1 = external synchronization frequency is locked. 0 AC_OK R This flag is a programmable combination of other internal flags and refers to the condition of the input voltage. A value of 1 means that the output of the AC_OK pin is low. Table 149. Register 0xFE82—Latched Flag 2 Bits Bit Name R/W Description [7:6] RSVD R Reserved. 5 LOW_POWER R 1 = input power has dropped below the threshold for low power mode operation. 4 FAST_LOOP R 1 = fast loop compensation filter is in use. 3 VCORE_OV R 1 = an overvoltage condition is present on the VCORE rail. 2 VDD_3.3V_OV R 1 = an overvoltage condition is present on the VDD rail. 1 VDD_3.3V_UV R 1 = an undervoltage condition is present on the VDD rail. 0 RSVD R Reserved. PWM VALUE REGISTER Table 150. Register 0xFE84—PWM Value Bits Bit Name R/W Description [7:0] PWM value R Return the eight MSBs of the PWM value (10 bits). VAC_LINE_PERIOD REGISTER Table 151. Register 0xFE85—VAC_LINE_PERIOD Bits Bit Name R/W Description [7:0] VAC line period R Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs. READ TEMPERATURE ADC REGISTER Table 152. Register 0xFE86—Read Temperature ADC Bits Bit Name R/W Description [15:0] RTD temperature R Return the measured temperature in ADC 12-bit format. POWER METERING OFFSET TRIM FOR HIGH LINE INPUT REGISTER Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input Bits Bit Name R/W Description 7 Offset trim polarity R/W 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. [6:0] Power meter offset trim R/W This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds to 0.0625/128 of the full input power. |
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