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Data Sheet

ADP1047/ADP1048

Rev. 0 | Page 17 of 84

POWER FACTOR CORRECTION CONTROL LOOP

The ADP1047/ADP1048 implement the average current mode

power factor correction control loop using a traditional multi-

plier approach. The implementation of the loop is digital, and

all the signals are converted from analog to digital before they

are processed by the control loop. Σ-Δ ADCs are used to achieve

high performance, cost-effective implementation. Each ADC

has its own dedicated voltage reference.

DIGITAL COMPENSATION FILTERS

The ADP1047/ADP1048 are digital PFC controllers with ac power

monitoring. They are implemented in the digital domain using

a dedicated state machine, which allows the user to program the

loop response specifically, with no need for external loop

compensation.

The detailed control loop configuration is illustrated in Figure 14.

VREF is the digital reference voltage setting; VFB is the sensed feed-

back voltage of the output. The difference between VREF and VFB

is processed first by the voltage loop filter (HV). Its output, VEA,

is then multiplied by the instantaneous rectified input voltage,

VAC, and divided by the square of the rms value of VAC. The result,

IREF, is used as the reference signal for the current. The output of

the current loop filter (HI) is the duty cycle command. The

mathematical expression is

_ RMS

REF

Both the voltage loop and current loop digital compensating

filters, HV(z) and HI(z), are programmable. The filter transfer

function in the digital domain is

()1

256

−

⎟

⎠

⎞

⎜

⎝

⎛ −

H(z)

where:

is the filter zero.

is the filter gain.

is related to the switching frequency.

The frequency gains and zero locations can all be programmed

individually to tailor the loop response to the application. It is

recommended that the Analog Devices, Inc., GUI software be

used to program the filter (see the Software GUI section). The

GUI displays the filter response in Bode plot format and can be

used to calculate all stability criteria for the power supply.

Optimized Compensation Filters

Instead of a single programmable compensation filter, the

ADP1047/ADP1048 offer the following filter presets so that

the dynamic response of the control loop can be tailored to

optimize different operating conditions.

•

Low line current filter

•

High line current filter

•

Fast voltage compensation filter

The ADP1047/ADP1048 can be configured to switch auto-

matically between the high and low line filters when the rms

value of the ac line crosses the programmed threshold between

the high and low lines. (The high line threshold is programmed

in Register 0xFE35; the low line threshold is programmed in

The ADP1047/ADP1048 check for the value of the rms input

voltage at each half line cycle. When a transition between the

high and low line threshold is detected, the part waits for four

full line cycles before switching to the correct filter at the zero

crossing of the input line cycle. This is done to avoid spurious

transitions due to a missing or distorted voltage line cycle.

During soft start, one of four combinations of filters can be

used, depending on whether the fast loop mode is enabled

and whether the high line or low line is detected for soft start

(see Table 8).

–

VFB

HV (z)

VREF

VEA

–

IREF

DUTY CYCLE

HI (z)

VAC

V2AC_RMS

Figure 14. Control Loop Digital Filters

Table 8. Summary of the PFC Digital Compensation Filters for Soft Start

Line Filter

Normal Compensation Filter

Fast Voltage Compensation Filter

High Line

High line current filter, normal voltage filter

High line current filter, fast voltage filter

Low Line

Low line current filter, normal voltage filter

Low line current filter, fast voltage filter

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