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AD9518-2ABCPZ 数据表(PDF) 49 Page - Analog Devices

部件名 AD9518-2ABCPZ
功能描述  6-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  64 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9518-2ABCPZ 数据表(HTML) 49 Page - Analog Devices

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Data Sheet
AD9518-2
Rev. C | Page 49 of 64
Reg.
Addr.
(Hex)
Bits
Name
Description
[2:0]
Prescaler P
Prescaler: DM = dual modulus and FD = fixed divide.
2
1
0
Mode
Prescaler
0
0
0
FD
Divide-by-1.
0
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
1
DM
Divide-by-4 (4/5 mode).
1
0
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
1
1
FD
Divide-by-3.
0x017
[7:2]
STATUS pin control
Selects the signal that is connected to the STATUS pin.
7
6
5
4
3
2
Level or
Dynamic
Signal
Signal at STATUS Pin
0
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
0
1
DYN
N divider output (after the delay).
0
0
0
0
1
0
DYN
R divider output (after the delay).
0
0
0
0
1
1
DYN
A divider output.
0
0
0
1
0
0
DYN
Prescaler output.
0
0
0
1
0
1
DYN
PFD up pulse.
0
0
0
1
1
0
DYN
PFD down pulse.
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified previously.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
0
1
1
1
LVL
Status REF1 frequency; active high.
1
0
1
0
0
0
LVL
Status REF2 frequency; active high.
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency; active high.
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active; active high.
1
0
1
1
1
1
LVL
LD pin comparator output; active high.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active
low.
1
1
0
1
1
1
LVL
Status of REF1 frequency; active low.
1
1
1
0
0
0
LVL
Status of REF2 frequency; active low.
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
Status of VCO frequency; active low.
1
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
1
0
LVL
Holdover active; active low.
1
1
1
1
1
1
LVL
LD pin comparator output; active low.



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