数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AD9518-2ABCPZ 数据表(PDF) 10 Page - Analog Devices

部件名 AD9518-2ABCPZ
功能描述  6-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  64 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9518-2ABCPZ 数据表(HTML) 10 Page - Analog Devices

Back Button AD9518-2ABCPZ Datasheet HTML 6Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 7Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 8Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 9Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 10Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 11Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 12Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 13Page - Analog Devices AD9518-2ABCPZ Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 64 page
background image
AD9518-2
Data Sheet
Rev. C | Page 10 of 64
SERIAL CONTROL PORT
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
µA
Input Logic 0 Current
110
µA
Input Capacitance
2
pF
SCLK (INPUT)
SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
µA
Input Logic 0 Current
1
µA
Input Capacitance
2
pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
10
nA
Input Logic 0 Current
20
nA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
2
ns
SCLK to SDIO Hold, tDH
1.1
ns
SCLK to Valid SDIO and SDO, tDV
8
ns
CS to SCLK Setup and Hold, tS, tH
2
ns
CS Minimum Pulse Width High, tPWH
3
ns
PD, SYNC, AND RESET PINS
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
These pins each have a 30 kΩ internal pull-up
resistor
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
1
µA
Logic 0 Current
110
µA
Capacitance
2
pF
RESET TIMING
Pulse Width Low
50
ns
SYNC TIMING
Pulse Width Low
1.5
High speed
clock cycles
High speed clock is CLK input signal



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com