AD9518-2ABCPZ datasheet(57/64 Pages) AD

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Data Sheet

AD9518-2

Rev. C | Page 57 of 64

Reg.

Addr.

(Hex)

Bits

Name

Description

0x195

Divider 1 direct to output

Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.

0: OUT2 and OUT3 are connected to Divider 1 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 01b, there is no effect.

Divider 1 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x196

[7:4]

Divider 2 low cycles

Number of clock cycles (minus 1) of the divider input during which divider output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

Divider 2 high cycles

Number of clock cycles (minus 1) of the divider input during which divider output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x197

Divider 2 bypass

Bypasses and powers down the divider; route input to divider output.

0: uses divider (default).

1: bypasses divider.

Divider 2 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 2 force high

Forces divider output to high. This requires that the Divider 2 nosync bit (Bit 6) also be set.

This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.

0: divider output forced to low (default).

1: divider output forced to high.

Divider 2 start high

Select clock output to start high or start low.

0: starts low (default).

1: starts high.

[3:0]

Divider 2 phase offset

Phase offset (default = 0x0).

0x198

Divider 2 direct to output

Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.

0: OUT4 and OUT5 are connected to Divider 2 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.

If Register 0x1E1[1:0] = 01b, there is no effect.

Divider 2 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Table 47. VCO Divider and CLK Input

Reg.

Addr

(Hex)

Bits

Name

Description

0x1E0

[2:0]

VCO divider

Divide

4 (default).

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

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