TNETX3190 datasheet(57/66 Pages) TI1

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TNETX3190

ThunderSWITCH

™ 16/3 ETHERNET™ SWITCH

WITH 16 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS046B – FEBRUARY 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

SDRAM subcycle

operating characteristics over recommended operating conditions (see Figure 17)

NO.

PARAMETER

MIN

MAX

UNIT

tc(DCLK)

Cycle time, DCLK

tw(DCLKL)

Pulse duration, DCLK low

tw(DCLKH)

Pulse duration, DCLK high

td(DCLK)

Delay time, from DA, DRAS, DCAS, and DW valid to DCLK

↑

td(DA)

Delay time, from DCLK

↑ to DA, DRAS, DCAS, and DW invalid

ten(DDW)

Enable time, from DCLK

↑ to before DD31–DD00 driven (write cycle)

ten(DDR)

Enable time, from DCLK

↑ to before DD31–DD00 driven (read cycle)

tdis(DDW)

Disable time, from DCLK

↑ to after DD31–DD00 (after final write cycle) to Z state

tdis(DDR)

Disable time, from DCLK

↑ to after DD31–DD00 (after final read cycle) to Z state

td(DDW)1

Delay time, from DD valid to DCLK

↑ (write cycle)

td(DDW)2

Delay time, from DCLK

↑ to DD31–DD00 Z state (write cycle)

td(DDR)1

Delay time, from DCLK

↑ to DD31–DD00 valid (read cycle)

td(DDR)2

Delay time, from DCLK

↑ to DD31–DD00 invalid (read cycle)

Transition time, rise and fall, all signals

DCLK

(output)

DA13–DA00

DRAS

DCAS

(outputs)

DD31–DD00

(during writes)

(output)

DD31–DD00

(during reads)

(input)

Figure 17. SDRAM Subcycle

TNETX3190 数据表(PDF) 57 Page - Texas Instruments

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