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TNETX3190 数据表(PDF) 7 Page - Texas Instruments |
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TNETX3190 数据表(HTML) 7 Page - Texas Instruments |
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7 / 66 page  TNETX3190 ThunderSWITCH ™ 16/3 ETHERNET™ SWITCH WITH 16 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS046B – FEBRUARY 1998 – REVISED APRIL 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (ports 16–18)† TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M16COL M17COL M18COL 42 65 90 I Pulldown Collision sense. Assertion of MxxCOL in half-duplex signal indicates a network collision on that port. In full-duplex operation, transmission of new frames does not start if this terminal is asserted. M16CRS M17CRS M18CRS 43 66 92 I Pulldown Carrier sense. MxxCRS indicates a frame carrier signal is being received. M16FORCE10 M17FORCE10 M18FORCE10 54 80 104 I/O‡ Pullup Speed selection (force 10 Mbit/s is active low) – If pulled low by either the TNETX3270 or a PHY, the port operates at 10 Mbit/s. – If not pulled low by either the TNETX3270 or a PHY, the internal pullup resistor holds this signal high and the port operates at 100 Mbit/s. An external 4.7-k Ω pullup resistor connected to VDD(3.3V) may be required, depending on the system layout. M16LINK M17LINK M18LINK 52 78 102 I Pulldown Connection status. MxxLINK indicates the presence of a port connection. – If MxxLINK = 0, there is no link. – If MxxLINK = 1, the link is good. M16FORCEHD M17FORCEHD M18FORCEHD 53 79 103 I/O‡ Pullup Duplex selection (force half duplex is active low) – If pulled low by either the TNETX3270 or the PHY, the port operates at half duplex. – If not pulled low by either the TNETX3270 or the PHY, the internal pullup resistor holds this signal high and the port operates at full duplex. An external 4.7-k Ω pullup resistor connected to VDD(3.3V) may be required, depending on the system layout. M16RCLK M17RCLK M18RCLK 44 67 93 I Pullup Receive clock. Receive clock source from the attached PHY or PMI device. M16RXD3 M16RXD2 M16RXD1 M16RXD0 M17RXD3 M17RXD2 M17RXD1 M17RXD0 M18RXD3 M18RXD2 M18RXD1 M18RXD0 49 48 47 46 73 71 70 69 98 97 96 95 I Pullup Receive data (nibble receive data from the attached PHY or PMI device). Data on these signals is synchronous to MxxRCLK. MxxRXD0 is the least significant bit and MxxRXD3 is the most significant bit. M16RXDV M17RXDV M18RXDV 50 75 99 I Pulldown Receive data valid. When high, MxxRXDV indicates valid data is present on the MxxRXD3–MxxRXD0 lines. M16RXER M17RXER M18RXER 51 76 101 I Pulldown Receive error. MxxRXER indicates a coding error on received data. M16TCLK M17TCLK M18TCLK 33 56 82 I Pullup Transmit clock. Transmit clock source from the attached PHY or PMI device. † xx = ports 16, 17, and 18 ‡ Not a true bidirectional terminal. It can only be actively pulled down (open drain). |
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