TNETX3190 datasheet(6/66 Pages) TI1

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TNETX3190

ThunderSWITCH

™ 16/3 ETHERNET™ SWITCH

WITH 16 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS046B – FEBRUARY 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

10-Mbit/s MAC multiplexed interface (ports 00–15) is multiplexed into two groups (TH1 and TH2)

of eight ports†

TERMINAL

I/O

INTERNAL

DESCRIPTION

NAME

NO.

I/O

RESISTOR‡

DESCRIPTION

TH1CLK

TH2CLK

Pullup

Interface clock. Eight ports are supported on each interface and use this common 20-MHz

clock.

TH1COL

TH2COL

Pulldown

Interface collision sense. Assertion of THxCOL during half-duplex operation indicates

network collision on the current port. Additionally, during full-duplex operation, transmission

of new frames does not start if this terminal is asserted.

TH1CRS

TH2CRS

Pulldown

Interface carrier sense. THxCRS indicates a frame carrier signal is being received on a current

port.

TH1LINK

TH2LINK

Pulldown

Interface link presence. THxLINK indicates the presence of the connection on a port.

– Low = no link

– High = link good

TH1RENEG

TH2RENEG

233

None

Interface renegotiate. A 1-0-1 sequence output on THxRENEG causes flow control and

half/full duplex for a port to be renegotiated with its companion physical-layer (PHY) device.

These THxRENEG terminals connect to IFFORCEHD on TNETE2008.

TH1RXD3

TH1RXD2

TH1RXD1

TH1RXD0

TH2RXD3

TH2RXD2

TH2RXD1

TH2RXD0

Pullup

Interface receive data. The receive data nibble from the current port is synchronous to

THxCLK. When the THxRXDV signal is 1, the receive data terminals contain valid information.

THxRXD0 is the least significant bit and THxRXD3 is the most significant bit. These signals

also are used to report the channel state to the MAC.

TH1TXEN

TH2TXEN

240

None

Interface transmit enable. THxTXEN indicates valid transmit data on THxTXD.

TH1SYNC

TH2SYNC

Pullup

Interface synchronize. THxSYNC is used to synchronize the port traffic between the

media-access controller (MAC) and PHY. When THxSYNC is a 1, the current MAC-to-PHY

path is the multiplexer interface TH0, and the PHY-to-MAC path is the multiplexer interface

TH2. THxSYNC is sampled by the MAC on the falling edge of THxCLK.

TH1TXD3

TH1TXD2

TH1TXD1

TH1TXD0

TH2TXD3

TH2TXD2

TH2TXD1

TH2TXD0

239

237

236

234

None

Interface transmit data. The transmit data nibble for the current port is synchronous to

THxCLK. When THxTXEN is asserted, these signals carry data. THxTXD3–THxTXD0 are

used during renegotiation to convey flow-control and duplex configuration requests to the

PHY. THxTXD0 is the least significant bit and THxTXD3 is the most significant bit.

TH1RXDV

TH2RXDV

Pulldown

Interface receive data valid. When THxRXDV is a 1, it indicates that the THxRXD lines contain

valid data.

† THx = TH1 and TH2

‡ Internal resistors are provided to pull signals to known values. System designers should determine if additional pullups or pulldowns are required

in their system.

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