TNETA1500

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS021D – MARCH 1994 – REVISED JANUARY 1998

6

POST OFFICE BOX 655303

transmit operation (continued)

and C1 overhead bytes are not scrambled, and the scrambler is reset to 1111111 on the most-significant bit of

the byte immediately following the third C1 byte. The scrambler runs continuously throughout the complete

STS-3c frame.

After the STS-3c frame has been scrambled, the bytes are converted to a serial-data stream using a

parallel-to-serial converter. An APLL is used to generate the 155.52-MHz output clock from a 19.44-MHz

oscillator connected to TXREFCK. Two other sources can be used for the 155.52-MHz clock. CKGENBP and

CLKLOOP are used to select either a 155.52-MHz external clock source or the clock recovered from the

incoming serial-data stream APLL (loop timing). The functions for selecting the transmit-clock source are shown

in Table 2. The clock-generation APLL requires that an external 0.1-

µF capacitor be connected from CGCAP

to ground.

Table 2. Functions for CKGENBP and CLKLOOP

CKGENBP

CLKLOOP

CLOCK SOURCE

L

L

TXREFCK (19.44 MHz)

L

H

Receive recovered clock (loop timing)

H

H or L

TXHCKT, TXHCKC (155.52 MHz)

Both true and complementary pseudo-ECL-compatible serial data and clock outputs are available. The serial

data is output on the rising edge of the true clock signal (falling edge of the complement clock). The outputs are

designed to drive a 50-

Ω line terminated through a 50-Ω resistor to 3 V (or its equivalent).

A terminal-loopback feature is also provided on the device. When the terminal-loopback input is high, the ATM

cells received on the transmit input are looped back to the receive output. The ATM cells received are blocked.

The transmit operation is not affected in this mode and operates as previously described.

receive operation

The receive serial inputs to the TNETA1500 consist of 155.52-Mbit/s true and complementary PECL data and

an optional 155.52-MHz true and complementary pseudo-ECL clock. The 155.52-MHz clock inputs are needed

only if the clock-recovery-bypass input (CKRECBP) is high, which disables the clock-recovery circuit. This

feature is used typically for test purposes and normally is not used in a system application.

The clock-recovery circuit is used to recover the embedded clock signal from the serial nonreturn-to-zero (NRZ)

data inputs RSDT and RSDC. The clock-recovery circuit consists of a transition detector, an APLL, and a

retiming circuit. The transition detector is used to double the frequency of the incoming serial-data stream. This

is necessary because the NRZ-data stream does not contain a second harmonic, which is necessary to recover

the transmit clock. The APLL consists of a phase-frequency detector, a charge pump/loop filter, and an internal

voltage-controlled oscillator (VCO). The phase-frequency detector compares the output of the transition

detector to the output of the VCO and generates a signal to the charge pump/loop filter that is used to change

the frequency of the VCO. The frequency of the VCO is adjusted until it matches the frequency of the transition

detector. When this occurs, the APLL is locked to the frequency of the embedded clock signal.

The clock-recovery circuit also contains a circuit that retimes the input serial data to the recovered output clock.

The only external component required for the clock-recovery circuit is a 0.1-

µF capacitor that is connected from

CRCAP to ground. This capacitor is part of the charge-pump/loop-filter circuit.