TNETA1500

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS021D – MARCH 1994 – REVISED JANUARY 1998

9

POST OFFICE BOX 655303

receive operation (continued)

After descrambling, the ATM cell is passed to the output buffer, which operates as a FIFO. The receive-cell

interface consists of the output data (RD0–RD7), receive-clock input (RCKI), receive-read-enable input (RRE),

receive-FIFO-empty output (RXFE), beginning-of-ATM-cell indicator (RXCELL), and loss-of-receive-data

alarm (LOSRD). Data is sent out from the device on the rising edge of RCKI when RRE is low. The LOSRD alarm

goes active when the output FIFO overflows. In this case, the last cell placed into the FIFO is overwritten. The

output FIFO holds three complete ATM cells.

Cumulative counts of receive B1, B2, and B3 errors are provided by registers accessible through the controller

interface. These registers maintain running totals of B1, B2, and B3 block errors and coding violations. The

block-error counters maintain a count of the number of frames that are received with B1, B2, and B3 errors. The

coding-violation counters count the exact number of B1, B2, and B3 bit-interleaved parity (BIP) errors that occur.

It is possible for a single frame to contain 8 B1, 24 B2, and 8 B3 BIP errors. When any of the block-error or

coding-violation counters reach maximum count, a bit is set in the interrupt registers and an interrupt is

generated. These counters are rollover counters that roll over to zero after the maximum count occurs and an

interrupt is generated (see the controller-interface operation section for additional information).

When the receive side enters an LOCA state, a path RDI may need to be sent out the transmit side through the

outgoing G1 byte. A path-RDI alarm is declared when an LOCA state is persistent for an amount of time (also

known as soak time) that has not yet been specified by any industry standards. To provide maximum flexibility

with regard to this unspecified soak time, an 8-bit counter is provided through the controller interface that allows

the user to program the amount of soak time for a path-RDI alarm in increments of 125

µs. This counter is preset

(when a device reset occurs) to a value of 4 ms, which is the anticipated soak time for a path-RDI alarm.

controller-interface operation

The controller interface provides access to the internal memory locations that contain the control registers,

interrupt registers, interrupt-mask registers, and the ID register. Table 3 shows a memory map of the locations

of the various registers in the TNETA1500.

Table 3. TNETA1500 Register-Memory Map

ADDRESS

(HEX VALUE)

REGISTER

ADDRESS

(HEX VALUE)

REGISTER

00

Interrupt register 1

0D

B1 block-error counter

01

Interrupt register 2

0E

Not implemented

02

Interrupt register 3

0F

B2 block-error counter

03

ID register

10

Not implemented

04

Not implemented

11

B3 block-error counter

05

Control register 1

12

B1 coding-violation counter (LSB)

06

Control register 2

13

B1 coding-violation counter (MSB)

07

Interrupt-mask register 1

14

B2 coding-violation counter (LSB)

08

Interrupt-mask register 2

15

B2 coding-violation counter

09

Interrupt-mask register 3

16

B2 coding-violation counter (MSB)

0A

Multierrored cell counter

17

B3 coding-violation counter (LSB)

0B

Path-RDI soak counter

18

B3 coding-violation counter (MSB)

0C

Not implemented

>18

Not implemented