TNETA1500A

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS042A – AUGUST 1997 – REVISED JANUARY 1998

5

POST OFFICE BOX 655303

transmit operation (continued)

Table 1. Transmit Transport-Overhead and Path-Overhead Bytes

OVERHEAD BYTE

SONET FRAME

VALUE WHEN

SDHENABLE = LOW

SDH FRAME

VALUE WHEN

SDHENABLE = HIGH

A1

1111 0110 (F6h)

1111 0110 (F6h)

A2

0010 1000 (28h)

0010 1000 (28h)

C1 bytes

01 02 03 (h)

01 00 00 (h)

B1

B2

Calculated

Calculated

B3

First H1

0110 0010 (62h)

0110 1010 (6Ah)

Second H1 (H1*)

1001 0011 (93h)

1001 1011 (9Bh)

Third H1 (H1*)

1001 0011 (93h)

1001 1011 (9Bh)

First H2

0000 1010 (0Ah)

0000 1010 (0Ah)

Second H2 (H2*)

1111 1111 (FFh)

1111 1111 (FFh)

Third H2 (H2*)

1111 1111 (FFh)

1111 1111 (FFh)

Three H3 bytes

0000 0000 (00h)

0000 0000 (00h)

First K2

Normal operation: 0000 0000

Line FERF: 0000 0110

Normal operation: 0000 0000

Line FERF: 0000 0110

Third Z2

B2 error count:

0000 0000–0001 1000

B2 error count:

0000 0000–0001 1000

J1

0000 0000

0000 0000

C2

0001 0011

0001 0011

G1

Bits 1–4

B3 error count:

0000–1000

Path FERF:

1001

B3 error count:

0000–1000

Path FERF:

1001

G1

Bit 5

Path RDI: 1

Path RDI: 1

Bits 6–8

000

000

H4

0000 0000

0000 0000

and C1 overhead bytes are not scrambled, and the scrambler is reset to 1111111 on the most-significant bit of

the byte immediately following the third C1 byte. The scrambler runs continuously throughout the complete

STS-3c frame.

After the STS-3c frame has been scrambled, the bytes are converted to a serial-data stream using a

parallel-to-serial converter. An APLL is used to generate the 155.52-MHz output clock from a 19.44-MHz

oscillator connected to TXREFCK. Two other sources can be used for the 155.52-MHz clock. CKGENBP and

CLKLOOP are used to select either a 155.52-MHz external clock source or the clock recovered from the

incoming serial-data stream APLL (loop timing). The functions for selecting the transmit-clock source are shown

in Table 2. The clock-generation APLL requires that an external 0.01-

µF capacitor be connected from CGCAP

to ground.