TNETA1500A

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS042A – AUGUST 1997 – REVISED JANUARY 1998

9

POST OFFICE BOX 655303

controller-interface operation

The controller interface provides access to the internal memory locations that contain the control registers,

interrupt registers, interrupt-mask registers, and the ID register. Table 3 shows a memory map of the locations

of the various registers in the TNETA1500A.

Table 3. TNETA1500A Register-Memory Map

ADDRESS

(HEX VALUE)

REGISTER

ADDRESS

(HEX VALUE)

REGISTER

00

Interrupt register 1

0D

B1 block-error counter

01

Interrupt register 2

0E

Not implemented

02

Interrupt register 3

0F

B2 block-error counter

03

ID register

10

Not implemented

04

Not implemented

11

B3 block-error counter

05

Control register 1

12

B1 coding-violation counter (LSB)

06

Control register 2

13

B1 coding-violation counter (MSB)

07

Interrupt-mask register 1

14

B2 coding-violation counter (LSB)

08

Interrupt-mask register 2

15

B2 coding-violation counter

09

Interrupt-mask register 3

16

B2 coding-violation counter (MSB)

0A

Multierrored cell counter

17

B3 coding-violation counter (LSB)

0B

Path-RDI soak counter

18

B3 coding-violation counter (MSB)

0C

Not implemented

>18

Not implemented