TNETA1500A

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS042A – AUGUST 1997 – REVISED JANUARY 1998

6

POST OFFICE BOX 655303

transmit operation (continued)

Table 2. Functions for CKGENBP and CLKLOOP

CKGENBP

CLKLOOP

CLOCK SOURCE

L

L

TXREFCK (19.44 MHz)

L

H

Receive recovered clock (loop timing)

H

H or L

TXHCKT, TXHCKC (155.52 MHz)

Both true and complementary pseudo-emitter-coupled logic (PECL)-compatible serial data and clock outputs

are available. The serial data is output on the rising edge of the true clock signal (falling edge of the complement

clock). The outputs are designed to drive a 50-

Ω line terminated through a 50-Ω resistor to 3 V (or its equivalent).

A terminal-loopback feature also is provided on the device. When the terminal-loopback input is high, the ATM

cells received on the transmit input are looped back to the receive output. The ATM cells received are blocked.

The transmit operation is not affected in this mode and operates as previously described.

receive operation

The receive serial inputs to the TNETA1500A consist of 155.52-Mbit/s true and complementary PECL data and

an optional 155.52-MHz true and complementary PECL clock. The 155.52-MHz clock inputs are needed only

if the clock-recovery-bypass input (CKRECBP) is high, which disables the clock-recovery circuit. This feature

is used typically for test purposes and normally is not used in a system application.

The clock-recovery circuit is used to recover the embedded clock signal from the serial nonreturn-to-zero (NRZ)

data inputs RSDT and RSDC. The clock-recovery circuit consists of a transition detector, an APLL, and a

retiming circuit. The transition detector is used to double the frequency of the incoming serial-data stream. This

is necessary because the NRZ-data stream does not contain a second harmonic, which is necessary to recover

the transmit clock. The APLL consists of a phase-frequency detector, a charge pump/loop filter, and an internal

voltage-controlled oscillator (VCO). The phase-frequency detector compares the output of the transition

detector to the output of the VCO and generates a signal to the charge-pump/loop filter that is used to change

the frequency of the VCO. The frequency of the VCO is adjusted until it matches the frequency of the transition

detector. When this occurs, the APLL is locked to the frequency of the embedded clock signal.

The clock-recovery circuit also contains a circuit that retimes the input serial data to the recovered output clock.

The only external component required for the clock-recovery circuit is a 330-pF capacitor that is connected from

CRCAP to ground. This capacitor is part of the charge-pump/loop-filter circuit.

The clock signal recovered from the incoming serial-data stream also can be used as the transmit clock for the

transmit section. This is known as clock looping. The advantage of using the recovered receive clock as the

transmit clock is that the transmit clock is frequency locked to the same clock source that is used to generate

the incoming data stream. If this clock source provides a highly accurate low-parts-per-million clock, the transmit

clock also is a very accurate clock. The drawback to using clock looping is that if the receive signal is lost for

any reason, the transmit clock also is lost.

A facility-loopback (FLB) input loops the input data and recovered clock to the transmit output data and clock.

This provides a method of testing the function of the clock-recovery circuit and its jitter performance. It also can

be used for system-loopback testing.

The PECL inputs FLAGT and FLAGC are provided for interfacing to the loss-of-optical-signal outputs on optical

receivers. If the optical signal is lost, the loss-of-optical-carrier bit in the interrupt register is set and the interrupt

output (INTR) becomes active low.

The recovered clock signal and retimed input data are passed from the clock-recovery circuit to the framing

circuit. The framing circuit searches for the SONET framing bytes A1 and A2, where A1 has a set value of F6h

and A2 has a value of 28h. The exact framing pattern for an STS-3c frame is A1A1A1A2A2A2

(F6F6F6282828h). These bytes are not scrambled by the transmitter.