TNETA1500A

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS042A – AUGUST 1997 – REVISED JANUARY 1998

7

POST OFFICE BOX 655303

receive operation (continued)

The TNETA1500A provides loss-of-signal (LOS), out-of-frame (OOF), and loss-of-frame (LOF) alarms in

accordance with BellCore specification TR-NWT-000253, Issue 2, December 1991. The LOS alarm goes active

when no transitions are detected on the receive serial data for 3.3

µs. The LOS alarm goes inactive when two

consecutive framing patterns have been detected, and during the intervening time (one frame time), no

transitionless 3.3-

µs period is detected. The OOF alarm goes active when four consecutive-errored framing

patterns are received. The OOF alarm clears when two successive error-free framing patterns are received.

If the OOF condition fails to clear within 3 ms, the LOF alarm goes active. The LOF alarm goes inactive when

eight consecutive error-free SONET frames are identified. The LOS, OOF, and LOF alarms are indicated by

external signals and by setting a bit in the interrupt registers. This causes INTR of the controller interface to go

active low, signaling an interrupt.

After the SONET frame is established and the serial data converted to byte-wide data, the B1 BIP-8 parity is

calculated over the scrambled SONET frame. This value is compared with the value of B1 contained in the next

(n + 1) frame. The value of B1 calculated over the previous frame (n – 1) is compared to the value B1 in this

frame (frame n). If the two values do not match, B1ERR goes active, denoting that a B1 parity error has occurred.

In addition, the B1 parity-error bit in the interrupt register is set and INTR goes active low.

Next, the SONET frame is unscrambled (except for the A1, A2, and C1 bytes, which were not scrambled by the

transmitter). The B2 BIP-24 value is calculated over all the bits of the line overhead and the STS-3c envelope

capacity and compared to the value contained in the next frame. If a B2 parity error occurs, the B2 parity-error

bit in the interrupt register is set and INTR goes active low to notify the controller that a parity error has occurred.

The TNETA1500A monitors the receive K2 byte for line alarm-indication signal (LAIS) and line far-end receive

failure (LFERF) alarms. A LAIS alarm occurs when bits 6–8 of the receive K2 byte are set to a value of 111 for

five consecutive frames. The LAIS alarm goes inactive when bits 6–8 of the receive K2 byte are set to any value

other than 111 for five consecutive frames. The LFERF alarm goes active when bits 6–8 of the receive K2 byte

are set to a value of 110 for five consecutive frames. The LFERF alarm goes inactive when bits 6–8 of the receive

K2 byte are set to any value other than 110 for five consecutive frames. Both the LAIS and LFERF alarms are

indicated on an external terminal and by setting a bit in interrupt register 2.

The location of the J1 byte in the SPE is determined from the H1 and H2 bytes in the TOH. The location of the

J1 byte does not change from the previous frame unless the first four bits of H1 are set to 1001 (the new-data

flag) or the pointer value contained in H1 and H2 is different for three consecutive frames. The location of J1

also can be incremented or decremented by a 1-byte position by inverting certain bits in the H1 and H2 byte

pointer. If bits 7, 9, 11, 13, and 15 are inverted, the location of J1 is incremented one time slot. If bits 8, 10, 12,

14, and 16 are inverted, the location of J1 is decremented one time slot. Subsequent pointers contain the

new offset.

The TNETA1500A provides a loss-of-pointer (LOP) alarm to indicate that either an invalid pointer was detected

in the incoming H1 and H2 bytes or a new-data flag (NDF) (set to a value of 1001 — the first four bits of H1)

was found in eight consecutive frames. The LOP alarm goes inactive when a valid pointer with the NDF set to

0110 is detected in three consecutive frames. The device also provides a path-AIS alarm to indicate that a

path-AIS condition has been detected in the H1 and H2 bytes. A path-AIS condition is detected as an all-1s

condition in bytes H1 and H2 for three consecutive frames. The path-AIS alarm goes inactive when a valid

pointer, with the NDF set to 0110, is detected for three consecutive frames. The LOP alarm is not set if a path-AIS

condition is detected. The LOP alarm is indicated by an external signal and by the interrupt register. The

path-AIS alarm is indicated only by the interrupt register.

The B3 BIP-8 byte is calculated over the contents of the STS-3c SPE, which begins with the J1 byte. The value

calculated for B3 is compared with the value found in the next frame. If a B3 parity error occurs, the B3

parity-error bit is set in the interrupt register and INTR goes active low to notify the controller.