TNETA1500A

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS042A – AUGUST 1997 – REVISED JANUARY 1998

8

POST OFFICE BOX 655303

receive operation (continued)

The TNETA1500A monitors the receive G1 byte for a path far-end receive failure (FERF) and path

remote-defect indication (RDI) alarms. A path FERF occurs when bits 1–4 of the G1 byte are set to a value of

1001. The path FERF alarm goes inactive when bits 1–4 of the G1 byte are set to a non-1001 value. A path RDI

occurs when bit 5 of the G1 byte is set to a value of 1 for ten consecutive frames. The path RDI alarm goes

inactive when bit 5 of the G1 byte is set to a value of 0 for ten consecutive frames. Both the path FERF and path

RDI alarms are indicated through interrupt register 3.

Once the STS-3c SPE is located, the ATM cells are identified and extracted. Cell delineation is accomplished

by computing the HEC for the first four bytes after the J1 byte and comparing the calculated value with the fifth

byte. If the values do not match, the process advances one byte and then repeats. This process continues until

a match between the calculated value and the fifth byte occurs. Cell alignment is assumed to have occurred

when seven consecutive matches occur. Until cell alignment occurs, the loss-of-cell-alignment (LOCA) alarm

remains active. Once cell alignment is established, it is monitored constantly for a LOCA condition. A LOCA

condition is declared (LOCA goes active) when seven consecutive cells occur with header errors. At this point,

the hunting process starts over.

The receive side detects multiple-bit errors and corrects single-bit errors occurring in the 5-byte ATM header

of incoming ATM cells by using the HEC byte. This feature is deactivated by setting a bit in control register 1

(see Table 6). The ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1

(see Table 6) to disable the dropping of cells with uncorrectable errors. An 8-bit saturating counter (accessible

through the controller interface) counts the number of ATM cells with multiple-bit ATM-header errors.

After the ATM cells are extracted, they are descrambled. The 48-byte payload in the ATM cell is scrambled at

so that it can be sent to the next device.

The TNETA1500A has the capability of dropping idle and unassigned cells from the receive-data stream. An

idle cell is defined as a cell with a 5-byte ATM header set to a value of 00 00 00 01 52 (hex) and an unassigned

cell is defined as a cell with a 5-byte header of 00 00 00 00 55 (hex). In both cases, the payload is ignored. The

dropping of idle and/or unassigned cells can be disabled through control register 1 (CR1) in the

controller interface.

After descrambling, the ATM cell is passed to the output buffer, which operates as a FIFO. The receive-cell

interface consists of the output data (RD0 – RD7), receive-clock input (RCKI), receive-read-enable (RRE) input,

receive-FIFO-empty (RXFE) output, beginning-of-ATM-cell indicator (RXCELL), and loss-of-receive-data

(LOSRD) alarm. Data is sent out from the device on the rising edge of RCKI when RRE is low. The LOSRD alarm

goes active when the output FIFO overflows. In this case, the last cell placed into the FIFO is overwritten. The

output FIFO holds three complete ATM cells.

Cumulative counts of receive B1, B2, and B3 errors are provided by registers accessible through the controller

interface. These registers maintain running totals of B1, B2, and B3 block errors and coding violations. The

block-error counters maintain a count of the number of frames that are received with B1, B2, and B3 errors. The

coding-violation counters count the exact number of B1, B2, and B3 BIP errors that occur. It is possible for a

single frame to contain 8 B1, 24 B2, and 8 B3 BIP errors. When any of the block-error or coding-violation

counters reach maximum count, a bit is set in the interrupt registers and an interrupt is generated. These

counters are rollover counters that roll over to zero after the maximum count occurs and an interrupt is generated

(see the controller-interface operation section for additional information).

When the receive side enters a LOCA state, a path RDI may need to be sent out the transmit side through the

outgoing G1 byte. A path-RDI alarm is declared when a LOCA state is persistent for an amount of time (also

known as soak time) that has not yet been specified by any industry standards. To provide maximum flexibility

with regard to this unspecified soak time, an 8-bit counter is provided through the controller interface that allows

the user to program the amount of soak time for a path-RDI alarm in increments of 125

µs. This counter is preset

(when a device reset occurs) to a value of 4 ms, which is the anticipated soak time for a path-RDI alarm.