TNETA1585

ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE

WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

SDNS041A – NOVEMBER 1996 – REVISED JULY 1998

18

POST OFFICE BOX 655303

parameter-memory interface

The parameter-memory interface on the TNETA1585 is used for interface to the external SRAM containing the

connection-state information and parameters required per channel. The interface consists of a 32-bit data bus,

a 16-bit address bus, an output-enable terminal, and a write-enable terminal. The interface also provides an

additional address terminal (PMAD15) that can be used with address terminal (PMAD15) to provide support

for SRAM bank switching. This allows the user to use two 32K

× 32 banks of SRAM instead of one 64K × 32

bank by using PMAD15 and PMAD15 as chip selects. The TNETA1585 is designed to operate with a 15 ns or

faster asynchronous SRAM. The total SRAM requirement for parameter memory to support 2K connections

is 32K

× 32.

The parameter-memory information is accessed by the host via the slave interface. Details of the parameters

in parameter memory are found in the

TNETA1585 Programmer’s Reference Guide, literature number

SDNU016.

JTAG interface

The TNETA1585 supports boundary scan through a five-wire JTAG interface in accordance with IEEE Std

1149.1-1990 (includes IEEE Std 1149.1a-1993) IEEE Standard Test-Access Port and Boundary-Scan

Architecture.

The maximum operating frequency is 10 MHz for the JTAG interface.

JTAG instruction set

The TNETA1585 supports the following instructions:

INSTRUCTION

OP CODE (BINARY FORMAT)

EXTEST

000

IDCODE

100

SAMPLE/PRELOAD

001

BYPASS

111

INTERNAL SCAN

010

HIGH Z

101

idcode

VARIANT

PART NUMBER

MANUFACTURER

LSB

Bit number

31–28

27–12

11–1

0

Binary code

0000

TBD

00000010111

1