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TNETA1585 数据表(PDF) 21 Page - Texas Instruments

部件名 TNETA1585
功能描述  ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
PDF  32 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETA1585 数据表(HTML) 21 Page - Texas Instruments

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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
21
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
operating characteristics over recommended operating conditions (see Figure 4)
parameter-memory interface – write operation
NO.
PARAMETER
MIN
MAX
UNIT
1
td(PMAD)
Delay time, from CLOCK
↑ to PMAD15–PMAD0 valid
5
12
ns
2
td(PMDATA)
Delay time, from CLOCK
↑ to PMDATA31–PMDATA0 valid
5
12
ns
3
td(PMOE)
Delay time, from CLOCK
↑ to PMOE↑
5
13
ns
4
td(PMWE)1
Delay time, from CLOCK
↓ to PMWE↓
7
15
ns
5
td(PMWE)2
Delay time, from CLOCK
↓ to PMWE↑
7
15
ns
PMAD15–
PMAD0
(output)
PMOE
(output)
PMWE
(output)
PMDATA31–
PMDATA0
(output)
3
2
Valid
4
5
1
CLOCK
(input)
Valid
Z
Z
Figure 4. Parameter-Memory Interface – Write Operation



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