STA321MPL datasheet(14/50 Pages) STMICROELECTRONICS

14 / 50 page

Pin description

STA321MP

14/50

Doc ID 022647 Rev 1

Pin description

PDM interface clock (PDM_CLK)

The clock to the PDM interface is provided on this pin and will be used by the device to

sample the digital microphone data. This clock must be used to clock both the interface and

the microphones. The clock frequency must not exceed the upper limit of the microphone’s

specific clock frequency (please refer to the datasheet of the specific microphone used).

PDM input channels (PDMIN_1/6)

Audio information enters the device through the PDM input channels. These input pins

receive the digital output signal from the microphones.

RESET

Driving this pin low turns off the outputs and returns all settings to their defaults.

I2C bus

The SDA and SCL pins operate per the Phillips I2C specification. See Section 5: I2C bus

operation.

Phase-locked loop (PLL)

The phase-locked loop section provides the system timing signals and CKOUT.

Clock output (CKOUT)

System synchronization and master clocks are provided by CKOUT. This clock can be

conveniently divided and then used to clock both the PDM interface and the microphones.

Please refer to Figure 6.

PWM outputs (OUT1 through OUT8)

The PWM outputs provide the input signal for the power devices.

Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)

These are the outputs for audio information. Six different formats are available including I2S,

left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

Device power-down (PWDN)

Pulling PWDN low begins the power-down sequence which puts the STA321MP into a

low-power state. EAPD (pin 45 of the VFQFN-56 or pin 51 of the TQFP-64) goes low

approximately 30 ms later.

STA321MPL 数据表(PDF) 14 Page - STMicroelectronics