STA321MPL datasheet(28/50 Pages) STMICROELECTRONICS

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Registers

STA321MP

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Doc ID 022647 Rev 1

Setting the IDE bit enables this function, which looks at the input I2S data and will

automatically mute if the signals are perceived as invalid.

The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle.

The LDTE bit actively prevents double triggering of LRCLK.

The ECLE bit controls the device power down signal (EAPD) on clock loss detection. This

function is enabled by default. It is strongly recommended to avoid spurious noise during the

on-off sequence. The STA321MP has the ECLE bit set to 0.

7.2.7

Configuration register I (0x08)

This feature utilizes an ADC on SDI78 that provides power supply ripple information for

correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.

Bit

RST

Name

Description

4RW

IDE

Invalid input detect mute enable:

1: enable the automatic invalid input detect mute

Bit

RST

Name

Description

BCLE

Binary output mode clock loss detection enable

Bit

RST

Name

Description

LDTE

LRCLK double trigger protection enable

Bit

RST

Name

Description

ECLE

Auto EAPD on clock loss

EAPD

PSCE

Bit

RST

Name

Description

PSCE

Power supply ripple correction enable:

0: normal operation

1: PSCorrect operation

Bit

RST

Name

Description

EAPD

External amplifier power down:

0: external power stage power-down active

1: normal operation

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