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STA321MPL 数据表(PDF) 31 Page - STMicroelectronics

部件名 STA321MPL
功能描述  Scalable digital microphone processor
PDF  50 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA321MPL 数据表(HTML) 31 Page - STMicroelectronics

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STA321MP
Registers
Doc ID 022647 Rev 1
31/50
7.2.21
Channel 4 volume trim, mute, bypass (0x16)
7.2.22
Channel 5 volume trim, mute, bypass (0x17)
7.2.23
Channel 6 volume trim, mute, bypass (0x18)
7.2.24
Channel 7 volume trim, mute, bypass (0x19)
7.2.25
Channel 8 volume trim, mute, bypass (0x1A)
The volume structure of the STA321MP consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. There is also an additional offset for each channel called the channel volume trim.
The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an
example, if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for
channel 5 = XX dB. The channel volume trim is adjustable independently on each channel
from -10 dB to +10 dB in 1 dB steps. The master mute when set to 1 will mute all channels
at once, whereas the individual channel mutes (CnM) will mute only that channel. Both the
master mute and the channel mutes provide a "soft mute" with the volume ramping down to
mute in 8192 samples from the maximum volume setting at the internal processing rate
(~192 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any
channel volume register or the master volume register. When volume offsets are provided
via the master volume register, any channel whose total volume is less than -91 dB will be
muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration
register H) on a per-channel basis as this creates the smoothest possible volume
D7
D6
D5
D4
D3
D2
D1
D0
C4M
C4VBP
C4VT4
C4VT3
C4VT2
C4VT1
C4VT0
00
01
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C5M
C5VBP
C5VT4
C5VT3
C5VT2
C5VT1
C5VT0
00
01
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C6M
C6VBP
C6VT4
C6VT3
C6VT2
C6VT1
C6VT0
00
01
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C7M
C7VBP
C7VT4
C7VT3
C7VT2
C7VT1
C7VT0
00
01
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
C8M
C8VBP
C8VT4
C8VT3
C8VT2
C8VT1
C8VT0
00
01
00
0
0



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