STA321MPL datasheet(37/50 Pages) STMICROELECTRONICS

37 / 50 page

STA321MP

Registers

Doc ID 022647 Rev 1

37/50

7.2.38

Channel 7 and 8 output timing (0x36)

The centering of the individual channel PWM output periods can be adjusted by the output

timing registers. PWM slot settings can be chosen to ensure that pulse transitions do not

occur at the same time on different channels using the same power device. There are 8

possible settings, the appropriate setting varies based on the application and connections to

the FFX power devices.

7.2.39

Channel I2S output mapping channels 1 and 2 (0x37)

7.2.40

Channel I2S output mapping channels 3 and 4 (0x38)

7.2.41

Channel I2S output mapping channels 5 and 6 (0x39)

C8OT2

C8OT1

C8OT0

C7OT2

C7OT1

C7OT0

011

CnOT[2:0]

PWM slot

000

001

010

011

100

101

110

111

C2OM2

C2OM1

C2OM0

C1OM2

C1OM1

C1OM0

000

C4OM2

C4OM1

C4OM0

C3OM2

C3OM1

C3OM0

010

C6OM2

C6OM1

C6OM0

C5OM2

C5OM1

C5OM0

100

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