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STA321MPL 数据表(PDF) 16 Page - STMicroelectronics

部件名 STA321MPL
功能描述  Scalable digital microphone processor
PDF  50 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA321MPL 数据表(HTML) 16 Page - STMicroelectronics

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I2C bus operation
STA321MP
16/50
Doc ID 022647 Rev 1
address and if a match is found, it acknowledges the identification on SDA bus during the
9th-bit time. The byte following the device identification byte is the internal space address.
5.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA321MP acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA321MP again responds with an
acknowledgement.
5.3.1
Byte write
In the byte write mode the master sends one data byte, which is acknowledged by the FFX
core. The master then terminates the transfer by generating a STOP condition.
5.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4.
Write mode sequence
Figure 5.
Read mode sequence
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
AM045330v1
DEV-ADDR
ACK
START
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
W
R
T
R
A
T
S
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
W
R
T
R
A
T
S
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH
AM045331v1



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