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LRIS64K 数据表(PDF) 26 Page - STMicroelectronics |
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LRIS64K 数据表(HTML) 26 Page - STMicroelectronics |
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26 / 100 page  Data rate and data coding LRIS64K 26/100 Doc ID 15336 Rev 11 7.3 VCD to LRIS64K frames Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are implemented using code violation. Unused options are reserved for future use. The LRIS64K is ready to receive a new command frame from the VCD 311.5 µs (t2) after sending a response frame to the VCD. The LRIS64K takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the LRIS64K is ready to receive a command frame from the VCD. 7.4 Start of frame (SOF) The SOF defines the data coding mode the VCD is to use for the following command frame. The SOF sequence described in Figure 9 selects the 1 out of 256 data coding mode. The SOF sequence described in Figure 10 selects the 1 out of 4 data coding mode. The EOF sequence for either coding mode is described in Figure 11. Figure 9. SOF to select 1 out of 256 data coding mode Figure 10. SOF to select 1 out of 4 data coding mode Figure 11. EOF for either data coding mode AI06661 37.76µs 9.44µs 9.44µs 37.76µs AI06660 37.76µs 9.44µs 9.44µs 37.76µs 9.44µs AI06662 9.44µs 37.76µs 9.44µs |
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