SMB117 datasheet(5/32 Pages) SUMMIT

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SMB113A/B/SMB117/A

Preliminary Information

Summit Microelectronics, Inc

2111 2.6 9/16/2010

PIN DESCRIPTION

Pin Number

Pin Type

Pin Name

Pin Description

OUT

HSDRV_CH0

The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper

switching node of the channel 0 synchronous step-down buck

controller. Attach to the gate of p-channel MOSFET. A delay

exists between the assertion of HSDRV_CH0 and assertion of

LSDRV_CH0 to prevent excessive current flow during switching.

OUT

HEALTHY

(nRESET)

The HEALTHY pin is an open drain output. High when all

enabled output supplies are within the programmed levels.

HEALTHY will ignore any disabled supply.

There is a

programmable glitch filter on the under-voltage and over-voltage

sensors so that short transients outside of the limits will be

ignored by HEALTHY. This pin can also be programmed to act

as a Reset Output (nRESET). In this case, it releases with a

programmable delay after all outputs are valid. When used, this

pin should be pulled high by an external pull-up resistor.

COMP1_CH0

The COMP1_CH0 (Channel 0 primary Compensation) pin is the

primary feedback input of the channel 0 step-down buck

controller. The COMP1_CH0 pin is internally connected to a

programmable resistor divider.

COMP2_CH0

The COMP2_CH0 (Channel 0 secondary Compensation) pin is

the secondary feedback input of the channel 0 step-down buck

controller.

VM_CH0

The VM_CH0 (Channel 0 Voltage Monitor) pin connects the

channel 0 step-down controller output. Internally the VM_CH0 pin

connects to a programmable resistor divider.

I/O

SDA

SDA (Serial Data) is an open drain bi-directional pin used as the

2C data line. SDA must be tied high through a pull-up resistor.

SCL

SCL (Serial Clock) is an open drain input pin used as the I

clock line. SCL must be tied high through a pull-up resistor.

OUT

LSDRV_CH1

The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower

switching node of the channel 1 synchronous step-down buck

controller. Attach to the gate of n-channel MOSFET.

PWR

HVSUP1

Channel 1 High Voltage Supply for Channel 1 buck driver.

OUT

HSDRV_CH1

The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper

switching node of the channel 1 synchronous step-down buck

controller. Attach to the gate of p-channel MOSFET. A delay

exists between the assertion of HSDRV_CH1 and assertion of

LSDRV_CH1 to prevent excessive current flow during switching.

HOST_RESET

The HOST_RESET pin is an active high reset input. When this

pin is asserted high, the nRESET output will immediately go low.

When HOST_RESET is brought low, nRESET will go high after a

programmed reset delay. When pin 2 is used as a HEALTHY

output, this pin needs to be attached to GND or VBATT via a

resistor.

COMP1_CH1

The COMP1_CH1 (Channel 1 primary Compensation) pin is the

primary compensation input of the channel 1 step-down buck

controller. The COMP1_CH1 pin is internally connected to a

programmable resistor divider.

COMP2_CH1

The COMP2_CH1 (Channel 1 secondary Compensation) pin is

the secondary compensation input of the channel 1 step-down

buck controller.

SMB117 数据表(PDF) 5 Page - Summit Microelectronics, Inc.

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