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SMB117 数据表(PDF) 26 Page - Summit Microelectronics, Inc. |
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SMB117 数据表(HTML) 26 Page - Summit Microelectronics, Inc. |
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26 / 32 page ![]() SMB113A/B/SMB117/A Preliminary Information Summit Microelectronics, Inc 2111 2.6 9/16/2010 26 APPLICATIONS INFORMATION (CONTINUED) The input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. To ensure the maximum load current will not exceed the power rating of the FET, the power dissipation of each FET must be determined. It is important to look at each FET individually and then add the power dissipation of complementary FETs after the power dissipation over one cycle has been determined. The Power dissipation can be approximated as follows: Equation 3: ON L DSON T I R P * * ~ 2 Where TON is the on time of the primary switch. TON can be calculated as follows: Equations 4, 5: T V V PFET Buck T V V NFET Buck IN O IN O * : * ) 1 ( : − − − Compensation: Summit provides a design tool to called Summit Power Designer” that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. The power designer software can be found at http://www.summitmicro.com/prod_select/xls/SummitP owerDesigner_Install.zip. |
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