WM8253

Production Data

w

PD, Rev 4.1, August 2011

13

0

1

2

3

4

5

6

7

8

9

0

64

128

192

256

Gain register value (PGA[7:0])

0

0.5

1

1.5

2

2.5

3

0

64

128

192

256

Gain r e gis te r value (PGA[7:0])

Figure 7 PGA Gain Characteristic

Figure 8 Peak Input Voltage to Match ADC Full-scale Range

ADC INPUT BLACK LEVEL ADJUST

negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input

signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.

Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential

input voltage gives mid-range ADC output).

OVERALL SIGNAL FLOW SUMMARY

Figure 9 represents the processing of the video signal through the WM8253.

V

RESET

V

VRLC

V

3

CDS = 1

CDS = 0

VRLCEXT=1

260mV*(DAC[7:0]-127.5)/127.5

analog

-

X

+

+

V

OP[3:0]

D

1

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

D

2

CDS, VRLCEXT,RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

V

V

V

V

IN

x (65535/V

+0

if PGAFS[1:0]=11

+65535 if PGAFS[1:0]=10

+32767 if PGAFS[1:0]=0x

PGA gain

A = 0.78+(PGA[7:0]*7.57)/255

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 =65535-D1 if INVOP = 1

Offset

DAC

RLC

DAC

+

V

2

V

1

VRLCEXT=0

Figure 9 Overall Signal Flow

set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,