WM8253

Production Data

w

PD, Rev 4.1, August 2011

23

REGISTER

BIT

NO

BIT

NAME(S)

DEFAULT

DESCRIPTION

Setup

Register 5

0

VSMPDET

0

0 = Normal operation, signal on VSMP input pin is applied directly to

Timing Control block.

1 = Programmable VSMP detect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP input pin

and is applied to Timing Control block.

3:1

VDEL[2:0]

000

When VSMPDET = 0 these bits have no effect.

When VSMPDET = 1 these bits set a programmable delay from the

detected edge of the signal applied to the VSMP pin. The internally

generated pulse is delayed by VDEL MCLK periods from the detected

edge.

See Figure 13, Internal VSMP Pulses Generated for details.

4

POSNNEG

0

When VSMPDET = 0 this bit has no effect.

When VSMPDET = 1 this bit controls whether positive or negative edges

are detected:

0 = Negative edge on VSMP pin is detected and used to generate internal

timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate internal

timing pulse.

See Figure 13 for further details.

7:5

Reserved

000

Must be set to Zero

Setup

Register 6

0

Reserved

0

Must be set to Zero

2:1

Reserved

11

Must be set to One

4:3

OPDLY[1:0]

10

00 = 8ns

01 = 12ns

10 = 14ns

11 = not valid

7:5

Reserved

000

Must be set to zero

Offset DAC

(Red)

7:0

DACR[7:0]

10000000

Red channel offset DAC value. Used under control of the INTM[1:0] control

bits.

Offset DAC

(Green)

7:0

DACG[7:0]

10000000

Green channel offset DAC value. Used under control of the INTM[1:0]

control bits.

Offset DAC

(Blue)

7:0

DACB[7:0]

10000000

Blue channel offset DAC value. Used under control of the INTM[1:0]

control bits.

Offset DAC

(RGB)

7:0

DAC[7:0]

A write to this register location causes the red, green and blue offset DAC

registers to be overwritten by the new value

PGA gain

(Red)

7:0

PGAR[7:0]

00000000

Determines the gain of the red channel PGA according to the equation:

Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control

of the INTM[1:0] control bits.

PGA gain

(Green)

7:0

PGAG[7:0]

00000000

Determines the gain of the green channel PGA according to the equation:

Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under

control of the INTM[1:0] control bits.

PGA gain

(Blue)

7:0

PGAB[7:0]

00000000

Determines the gain of the blue channel PGA according to the equation:

Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control

of the INTM[1:0] control bits.

PGA gain

(RGB)

7:0

PGA[7:0]

A write to this register location causes the red, green and blue PGA gain

registers to be overwritten by the new value

Table 5 Register Control Bits