WM8253

Production Data

w

PD, Rev 4.1, August 2011

22

REGISTER MAP DESCRIPTION

The following table describes the function of each of the control bits shown in Table 4.

REGISTER

BIT

NO

BIT

NAME(S)

DEFAULT

DESCRIPTION

Setup

Register 1

0

EN

1

0 = complete power down, 1 = fully active.

1

CDS

1

Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode.

2

Reserved

0

Must be set to zero

3

Reserved

0

Must be set to Zero

5:4

PGAFS[1:0]

00

Offsets PGA output to optimise the ADC range for different polarity sensor

output signals. Zero differential PGA input signal gives:

00 = Zero output

(use for bipolar video)

01 = Zero output

10 = Full-scale positive output

(use for negative going video)

11 = Full-scale negative output

(use for positive going video)

6

MODE3

0

This bit must be set when operating in MODE3 (MCLK:VSMP=2:1) 0 =

other modes, 1 = MODE3.

NB, when in this mode the CDSREF bits should also be set to 01 to allow

clamping to operate correctly.

7

Reserved

0

Must be set to zero

Setup

Register 2

1:0

Reserved

11

Must be set to One

2

INVOP

0

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative-going video gives positive going output data.

3

VRLCEXT

0

When set powers down the RLCDAC, changing its output to Hi-Z, allowing

VRLC/VBIAS to be externally driven.

4

Reserved

0

Must be set to Zero

5

RLCDACRNG

1

Sets the output range of the RLCDAC.

0 = RLCDAC ranges from 0 to VDD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximately).

7:6

DEL[1:0]

00

Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC

clock period = 3 MCLK periods.

00 = Minimum latency

01 = Delay by one ADC clock

period

10 = Delay by two ADC clock periods

11 = Delay by three ADC clock periods

Setup

Register 3

3:0

RLCV[3:0]

1111

Controls RLCDAC driving VRLC pin to define single ended signal

reference voltage or Reset Level Clamp voltage. See Electrical

Characteristics section for ranges.

5:4

CDSREF[1:0]

01

CDS mode reset timing adjust.

00 = Advance 1 MCLK period

01 = Normal

10 = Retard 1 MCLK period

11 = Retard 2 MCLK periods

7:6

Reserved

00

Must be set to Zero

Software

Reset

Any write to Software Reset causes all cells to be reset.

It is recommended that a software reset be performed after a power-up

before any other register writes.

Setup

Register 4

2:0

Reserved

101

Must be set to ‘101’

3

INTRLC

0

This bit is used to determine whether Reset Level Clamping is enabled.

0 = RLC disabled, 1 = RLC enabled.

5:4

INTM[1:0]

00

Colour selection bits used in internal modes.

00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

See Table 1 for details.

7:6

Reserved

00

Must be set to Zero