WM8253SCDSSLASHV datasheet(14/27 Pages) WOLFSON

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WM8253

Production Data

PD, Rev 4.1, August 2011

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

the WM8253.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

VIN - VRESET ...................................................................... Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

VIN - VVRLC ....................................................................... Eqn. 2

If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

(VRLCSTEP  RLCV[3:0]) + VRLCBOT ..................................... Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + {260mV  (DAC[7:0]-127.5) } / 127.5 ...................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

V2  [0.78+(PGA[7:0]*7.57)/255] ..................................... Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[15:0] = INT{ (V3 /VFS)  65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6

D1[15:0] = INT{ (V3 /VFS)  65535}

PGAFS[1:0] = 11 ................

Eqn. 7

D1[15:0] = INT{ (V3 /VFS)  65535} + 65535 PGAFS[1:0] = 10 ................ Eqn. 8

where the ADC full-scale range, VFS = 2.0V

if D1[15:0] < 0

D1[15:0] = 0

if D1[15:0] > 65535 D1[15:0] = 65535

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[15:0] = D1[15:0]

(INVOP = 0) .......................

Eqn. 9

D2[15:0] = 65535 – D1[15:0]

(INVOP = 1) .......................

Eqn. 10

WM8253SCDS/V 数据表(PDF) 14 Page - Wolfson Microelectronics plc

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