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WM8253SCDS/V 数据表(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8253SCDS/V 数据表(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 27 page ![]() WM8253 Production Data w PD, Rev 4.1, August 2011 15 OUTPUT DATA FORMAT The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 10 shows the output data formats for all modes. Table 2 summarises the output data obtained for each format. MCLK 4+4+4+4-BIT OUTPUT AB C D Figure 10 Output Data Formats (Modes 1, 3, 4) OUTPUT FORMAT OUTPUT PINS OUTPUT 4+4+4+4-bit (nibble) OP[3:0] A = d15, d14, d13, d12 B = d11, d10, d9, d8 C = d7, d6, d5, d4 D = d3, d2, d1, d0 Table 2 Details of Output Data Shown in Figure 10 |
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