AS3502 datasheet(8/29 Pages) AMSCO

8 / 29 page

REV. M

Page 8

September 1998

AS3502

PCM Level

8-Bit A-Law Format

16-Bit Linear Format

VIN =

+ Full Scale

1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 x x

VIN =

+0-Code

1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 x x

VIN =

-0-Code

0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x

VIN =

- Full Scale

0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x x

x: not used

The

interface

supports

short

and

long

strobe

synchronisation modes and full duplex synchronous

operations of both receive and transmit section. PCM

data is written into the transmit register and shifted

out in 8 or 16 clock cycles by the transmit shift

samples are converted into parallel format by the

receive shift register and hereafter buffered in the

receive latch. This double buffered hardware I/O

scheme

guarantees

minimum

port

latency

and

increased channel service time. Both shift registers

have separate strobe signals for asynchronous time

slot operation of transmit and receive channel and are

clocked by a common shift clock signal that may vary

from 64 kHz up to 4.096 MHz and that must be locked

to the master clock. The strobe signals have to be

synchronised to the shift clock and should have a

repetition rate of 8 kHz. ±50 ppm.

Short Strobe Mode

This is the default mode on powering up the device.

The transmit and receive strobe inputs must be one

bit shift clock long and have to be High during a falling

edge of the respective bit shift clocks (see PCM

Timing Diagramme) In the transmit section the next

rising edges of SCLK enable the TXD output buffer

and shift out PCM data bits. The falling edge of the

last bit shift clock SCLK disables the TXD output

buffer. In the receive section the next falling edge of

SCLK shifts in PCM data bits at RXD.

Long Strobe Mode

The serial port enters the long strobe mode if both

strobe pulses (TXS, RXS) are more than three bit

clock periods long (See PCM Timing Diagramme). In

the transmit section the next rising edge of SCLK or

TXS, whichever comes later, clocks out the first bit.

The effect of the transmit strobe occurring after the

shift clock is to shorten the first bit at the TXD output.

The following rising edges of the SCLK shift out the

remaining data bits. The TXD output is disabled by

the last falling SCLK edge or by the TXS signal going

Low, whichever comes later. In the receive section a

rising edge on the receive strobe input RXS will initi-

ate the PCM data on RXD pin to be shifted into the

receive shift register with the falling edges of SCLK.

Serial Control Interface

The internal operation of AS3502 is controlled by a 4-

wire serial port that is designed to write and read back

control and status information from any serial micro-

processor port. It consists of a 16 bit shift register with

8 address bits and 8 data bits. The first byte is the

Address Byte that is clocked in serially by asserting

the CS line for 8 clock cycles. The MSB address bit

in the address field defines whether the data transfer

is a write or a read operation. The second byte is the

Command Data Byte that is clocked in by keeping

Low for another 8 clock cycles. The address

decoder latches the address bits received into a

after

clock

cycles.

operates

fully

autonomously and constantly cycles through 3 states:

•

Load address decoder

•

Calculate address and type of data transfer

•

Data transfer

After decoding the data byte is latched into the de-

coded register during a write operation or retrieved

from the selected register during a read operation.

Data is retrieved by asserting the CS

line and by

shifting 8 address bits into the input shift register

through SDI. The next 8 clock cycles shift out the data

byte through SDO. The full shift register is shifted out

where the 8 MSB bits are shifted out as Hi-Z.

Data states on the SDO line can only change with the

falling edge of SCL. Data on the SDI line is shifted in

with the rising edge of SCL.

All commands are preceded by the start condition,

which is a High to Low transition of the CS line. The

AS3502 continuously monitors this line for the start

condition and does not respond to any command until

this condition has been met. CS may either be kept

Low for 16 clock cycles or may go High after 8 clock

cycles and go Low again for the next 8 clock cycles

when programming different register locations.

All communications are terminated by a stop condi-

tion, which is a Low to High transition of CS after 16

shift clock cycles. The stop condition is also used to

place the AS3502 serial control interface in the

standby power mode.

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