REV. M

Page 3

September 1998

AS3502

Pin Description (continued)

Pin #

Name

Type

Function

10

POR

DI

Power On Reset Input

An active Low signal on this pin starts the system initialization. All internal registers

are set to their default values and the serial interface will be reinitialized and the

chip will enter power down mode.

11

CS

DI

Serial Control Chip Select Input

An active Low signal on this pin enables serial data transfers via SDI and SDO.

12

SCL

DI

Serial Control Clock Input

This pin acts as shift clock signal input for serial control data transfer via SDI and

SDO when CS is active Low and may be asynchronous to all other clock signals.

13

SDI

DI

Serial Control Data Input

This input samples control data bits on the rising edges of the serial clock SCL

when CS is active Low. Depending on the type of transfer 8 or 16 bits are shifted

in.

14

SDO

DO

Serial Control Data Output

This output shifts out control/status data with the falling edge of SCL when CS is

active Low.

15

RXD

DI

Receive PCM Data Input

This input samples PCM data bits on the falling edges of the serial clock SCLK

following a rising edge on the receive strobe signal. After the time when all data

bits have been shifted into the receive shift register all bits are latched into the

receive latch for digital to analogue conversion.

16

RXS

DI

Receive PCM Strobe Input

The signal on this input initiates shifting of serial data into the receive shift register.

It must be synchronized with SCLK. The clock rate is typically 8 kHz. The signal

width determines whether short strobe or long strobe mode is used: A pulse width

of one to two shift clock periods selects short strobe mode. (For further information

see PCM Timing Diagramme ). The strobe signal does not need to be active

throughout the transmission period since an internal bit counter generates the

necessary timing for 8 or16 bit periods depending on the selected output format for

serial PCM reception.

17

TXS

DI

Transmit PCM Strobe Input

This signal on this input initiates shifting of serial data out of the transmit shift

register. It must be synchronized with SCLK. The clock rate is typically 8 kHz. The

signal width determines whether short strobe or long strobe mode is used: A pulse

width of one to two shift clock periods selects short strobe mode. Pulse widths

from 3 clock periods on wards select long strobe mode. The strobe signal does not

need to be active throughout the transmission period since an internal bit counter

generates the necessary timing for 8 or 16 bit periods depending on the selected

output format for serial PCM transmission.

18

TXD

DO

Transmit PCM Data Output

This Tristate output shifts out PCM data from the Codec's A/D converter and is

activated during the transmission of serial data for 8 or 16 transmit clock periods

following a rising edge on the transmit strobe signal. It is updated by the rising

edges of the SCLK clock signal. The output goes back to high impedance after

transmission of 8 or 16 data bits.