TTP/C-C2 Communication Controller – Preliminary Data Sheet

AS8202

Rev. 1.0, October 2000

Page 2 of 2

Key Features

• Dedicated controller supporting TTP/C (time triggered protocol class C)

• Suited for dependable distributed real-time systems with guaranteed response time

• Application fields: Automotive (by-wire braking, steering, vehicle dynamics control, drive

train control), Aerospace (aircraft electronic systems), Industrial systems, Railway systems

• TTP/C asynchronous data rate up to 5 MBit/s @ clock 40 MHz, synchronous data rate 25

MBit/s @ clock 40 MHz

• Single power supply 3.3V

• 0.35µm CMOS process

• Temperature range: -40°C to 125° C

• 2k x 16 RAM message, status and control area (communication network interface)

• RAM for instruction code and configuration data

• 16 Bit non-multiplexed host CPU interface

• 16 Bit RISC architecture

• 16k x 16 internal FLASH memory for firmware and scheduling information

• software tools, design-in support, development boards available ( http://www.tttech.com)

•

80 pin TQFP Package

General Description

The

AS8202

communications

controller

is

an

integrated

device

supporting

serial

communication according to the TTP/C specification. It performs all communications tasks such

as reception and transmission of messages in a TTP

CPU.

TTP

time systems. It provides following services:

• predictable transmission of messages with minimal jitter

• fault-tolerant distributed clock synchronisation

• consistent membership service with small delay

• masking of single faults

rxd[1:0]

rxclk[1:0]

rxdv[1:0]

rxer[1:0]

xin1

xout1

txd[1:0]

cts[1:0]

txclk[1:0]

test_se

ftest

stest

fidis

mtest

ram_data[15:0]

ram_address[11:0]

ram_ceb

ram_oeb

ram_web

ram_readyb

time_signalb

led[0]/time_tick

led[1]/time_overflow

led[2]/microtick

xin0

xout0

resetb

plloff

Quartz or

Oscillator

Controller

network

interface

(CNI)

TTP/C

protocol

processor core

Instruction

RAM memory

Network

configuration

memory

(MEDL)

TTP/C

Bus -

Media

Drivers

Bus

guardian

Receiver

Transmitter

Reset &

Time

base

Host

Processor

Interface

Test

Inter-

face

FLASH

memory

Figure 1 AS8202 Block Diagram