TTP/C-C2 Communication Controller – Preliminary Data Sheet

AS8202

Rev. 1.0, October 2000

Page 6 of 6

Output Pins

Pin Name

Vol

Voh

Iol (1)

Ioh(2)

Ioz(3)

NOTE

V

V

mA

mA

txd[0,1],cts[0,1],led[0,2]

0.4

2.4

4.0

-4.0

NA

CMOS output

All other output pins

(except xout0, xout1)

0.4

2.4

2.0

-2.0

NA

CMOS output

All I/O pins

0.4

2.4

2.0

-2.0

+/-10

CMOS output, Tristate

1.

Vol, Iol is tested at VDD = 3.3V

2.

Voh, Ioh is tested at VDD = 3.3V

3.

Ioz is tested at VDD = 3.6V

AC Characteristics

PARAMETER

SYMBOL

PIN

MIN

MAX

NOTE

main clock external operating

frequency

clkext

xin0

0

40 MHz

pin plloff = high

PLL not used

main clock XTAL0 frequency

clkxt0

xin0/xout0

1 MHz

20 MHz

main internal clock frequency

clk0

---

---

40 MHz

pin plloff = low PLL

XTAL1 operating frequency

clkxt1

xin1/xout1

1 MHz

20 MHz

1.

XTAL frequency or external clock frequency for PLL input is fixed to 10 MHz, other frequencies applicable only

without PLL function in use.