TTP/C-C2 Communication Controller – Preliminary Data Sheet

AS8202

Rev. 1.0, October 2000

Page 7 of 7

A pplication Information

Host CPU Interface

The host CPU interface also referred as CNI (communication network interface) connects the

application circuitry to the TTP controller. All ram_-lines provide asynchronous read/write

access to a dual ported RAM. There are no setup/hold constraints referred to the microtick

(main clock “clk0”). The signals have to be applied for certain duration to be synchronized to

the main internal clock (microtick). The time_-lines signal to host CPU the global synchronous

time of the TTP network and determine when to deliver, resp. to fetch data from the host

interface. One of the lines may be connected to an interrupt input of the host CPU. Note that

the microtick, time_overflow and the time_tick pins can be configured as general purpose

output LED pins (see the LED Interface section below).

Host Interface Ports

Pin Name

mode

width

comment

ram_address[0:11]

in

12

DPRAM address bus, 12 bit

ram_data[0:15]

inout (tri)

16

DPRAM data bus, 16 bit

ram_ceb

In

1

DPRAM chip enable

ram_web

In

1

DPRAM write enable

ram_oeb

In

1

DPRAM output enable

ram_readyb

out

1

DPRAM ready

time_overflow

out

1

Overflow of global time (global time is Zero)

microtick

out

1

Microtick (internal main clock)

time_signal

out

1

CNI time signal

time_tick

out

1

Macrotick (global time is incremented)

Asynchronous DPRAM interface

Signals ram_address[0:11] and ram_web have to be stable before the falling edge of ram_ceb

For a write access the host sets ceb, web, address and data until the DPRAM has taken the

data and set readyb active low. The next access may start with readyb inactive again. A read

cycle starts with valid address and ceb, the data is valid with readyb active low. A low level on

oeb and ceb switches the data bus from tristate to output. Access times depend on the

controller clock rate and controller activity, typical values are:

controller cycle time

Tc

Min 25 ns (40 MHz)

write time

Tw

Min 4 Tc

read time

Tr

Min 5 Tc

readyb low time

Trb

Min 1 Tc

Trb

Trb

xx

tristate

valid

valid

ceb

addres

data

web

oeb

ready

b

valid

valid

write

read

Tw

Tr