TTP/C-C2 Communication Controller – Preliminary Data Sheet

AS8202

Rev. 1.0, October 2000

Page 4 of 4

Pin Description

Pin

Name

Dir

Description

1,12,21,32,51,61,71

Vdd

P

positive power supply

4,13,24,33,43,52,62,72

Vss

P

Negative power supply

2

xout0

O

Main clock: analog pad from oscillator / leave open

when providing external clock

3

xin0

I

Main clock: analog pad from oscillator / use as input

when providing external clock

5

txd[0]

Transmit data channel 0

6

cts[0]

Transmit enable channel 0

7

txclk[0]

TTP/C synchronous: Transmit clock channel 0

8

rxer[0]

TTP/C synchronous: Receive error channel 0

9

rxclk[0]

TTP/C synchronous: Receive clock channel 0

10

rxdv[0]

TTP/C synchronous: Receive data valid channel 0

11

rxd[0]

Receive data channel 0

14

txd[1]

Transmit data channel 1

15

cts[1]

Transmit enable channel 1

16

txclk[1]

TTP/C synchronous: Transmit clock channel 1

17

rxer[1]

TTP/C synchronous: Receive error channel 1

18

rxclk[1]

TTP/C synchronous: Receive clock channel 1

19

rxdv[1]

TTP/C synchronous: Receive data valid channel 1

20

rxd[1]

Receive data channel 1

22

xout1

O

Bus guardian clock: analog pad from oscillator / leave

open when providing external clock

23

xin1

I

Bus guardian clock: analog pad from oscillator / use as

input when providing external clock

25

test_se

Test input, connect to Vss

26

stest

Test input, connect to Vss

27

plloff

PLL disable pin

28

ftest

Test input, connect to Vss

29

fidis

Test input, connect to Vss

30

resetb

I

main reset input signal, active low

31

time_signalb

CNI control signal, CNI time signal

34

led[0]/microtick

Configurable: either generic output port (f.e. to drive

LEDs) or timing signal TIME_TICK

35

led[1]/time_tick

Configurable: either generic output port (f.e. to drive

LEDs) or timing signal TIME_OVERFLOW

36

led[2]/time_overflow

Configurable: either generic output port (f.e. to drive

LEDs) or timing signal TIME_OVERFLOW

37

mtest

Test input, connect to Vss

38-42,44-50

ram_address[0:11]

I

Host interface (CNI) address bus

53-60,63-70

ram_data[0:15]

I/O

Host interface (CNI) data bus, tristate

73

ram_ceb

Host interface (CNI) chip enable, active low

74

ram_oeb

Host interface (CNI) output enable, active low

75

ram_web

Host interface (CNI) write enable, active low

76

ram_readyb

Host interface (CNI) transfer finish signal, active low

77

to Vss

P

Connect to Vss

78

to Vdd

Connect to Vdd

79

high Z

Do not connect

80

high Z

Do not connect

I

Input CMOS

Input CMOS with pull up

Input CMOS with pull down

O

Output CMOS

Output with pull up when tristate

I/O

Input/Output CMOS tristate

P

Power Pin