AD607

REV. 0

–17–

Bias System

a typical supply current of 8.5 mA at midgain and T = 27

°C,

corresponding to a power consumption of 25 mW. Any voltage

from 2.7 V to 5.5 V may be used.

The bias system includes a fast-acting active-high CMOS-

compatible power-up switch, allowing the part to idle at 550

µA

when disabled. Biasing is proportional-to-absolute-temperature

(PTAT) to ensure stable gain with temperature.

An independent regulator generates a voltage at the midpoint of

pedance. This voltage does not shut down, ensuring that the

major signal interfaces (e.g., mixer-to-IF and IF-to-demodula-

tors) remain biased at all times, thus minimizing transient dis-

turbances at power-up and allowing the use of substantial

decoupling capacitors on this node. The quiescent consumption

of this regulator is included in the idling current.

AD607

FDIN

50k

Ω

50k

Ω

VPOS

EXTERNAL

FREQUENCY

REFERENCE

a. Biasing FDIN from Supply when Using

External Frequency Reference

AD607

FDIN

50k

Ω

EXTERNAL

FREQUENCY

REFERENCE

VMID

b. Biasing FDIN from VMID when Using

External Frequency Reference

Figure 41. Suggested Methods for Biasing Pin FDIN

USING THE AD607

In this section, we will focus on a few areas of special impor-

tance and include a few general application tips. As is true of

any wideband high gain component, great care is needed in PC

board layout. The location of the particular grounding points

must be considered with due regard to possibility of unwanted

signal coupling, particularly from IFOP to RFHI or IFHI or both.

The high sensitivity of the AD607 leads to the possibility that

unwanted local EM signals may have an effect on the perfor-

mance. During system development, carefully-shielded test as-

semblies should be used. The best solution is to use a fully-

enclosed box enclosing all components, with the minimum

number of needed signal connectors (RF, LO, I and Q outputs)

in miniature coax form.

The I and Q output leads can include small series resistors

(about 100

Ω) inside the shielded box without significant loss of

performance, provided the external loading during testing is

light (that is, a resistive load of more than 20 k

Ω and capaci-

tances of a few picofarads). These help to keep unwanted RF

emanations out of the interior.

The power supply should be connected via a through-hole ca-

pacitor with a ferrite bead on both inside and outside leads.

Close to the IC pins, two capacitors of different value should be

pin, VMID. Guidance on these matters is also generally in-

cluded in applications schematics.

Gain Distribution

As in all receivers, the most critical decisions in effectively using

the AD607 relate to the partitioning of gain between the various

subsections (Mixer, IF Amplifier, Demodulators) and the place-

ment of filters, so as to achieve the highest overall signal-to-

noise ratio and lowest intermodulation distortion.

Figure 42 shows the main RF/IF signal path at maximum and

minimum signal levels.

Figure 42. Signal Levels for Minimum and Maximum Gain

IOUT

QOUT

I

Q

RFHI

LOIP

MXOP

IFHI

DMIP

IFOP

IF BPF

IF BPF

(VMID)

330

Ω

330

Ω

(TYPICAL

IMPEDANCE)

(LOCATION OF OPTIONAL

SECOND IF FILTER)

CONSTANT

–16dBm

(

±50mV)

±54mV

MAX INPUT

±1.3V

MAX OUTPUT

±54mV

MAX INPUT

±560mV

MAX OUTPUT

±154mV

MAX INPUT

±1.23V

MAX OUTPUT