AD607

REV. 0

–19–

of current exactly balances the 4.5

µA discharge current. (It

since the AGC filter is an integrator.)

Thus, at 20 mV/dB

V

IT

C

=

4.5

µA × 93 ns

1 nF

= 0.42 mV

This corresponds to 0.021 dB, and the ripple will modulate the

gain by that amount over each cycle. The effect of such modula-

tion on the signal is hard to quantify, but it roughly translates to

a 2% amplitude modulation. Also, the gain ripple depends on

the scale factor. For this example, at GREF = 1.23 V and a

16.4 mV/dB scale factor, the gain ripple increases to 0.025 dB.

AGC Charge Time

When the gain is too high, the IF amplifier will be overdriven to

produce a square wave output (roughly) of

±560 mV. If per-

fectly square and time- and amplitude-symmetric, this would be

sliced at the 300 mV level to generate a current of 76

µA/2, or

38

µA. After subtracting the 4.5 µA, we should have about 33 µA.

In fact, the maximum ramp-up current is about 20

µA, because

the waveform is not a crisp square wave (and as the loop ap-

proaches equilibrium it is more nearly sinusoidal). Thus, the

ramp-up rate is 20/4.5 = 4.4 times faster than the discharge rate.

In our example, a 1.6 V change will require about 1.5 ms using

C = 1 nF.

Applications Hints

Do not place a resistor from Pin 12 to Ground: The resistor

converts the integrator—ideal for AGC—into a low-pass filter.

An integrator needs no input to sustain a given output; a low-

pass filter does. This “input” is an INCREASED AMPLITUDE

required at IFOP. The AGC loop thus does not level the output

at IFOP.

Reasons for Using a Larger AGC Capacitor

1. In applications where gain modulation may be troublesome,

raise the capacitor from 1 nF to 2.7 nF; the 80 dB slew time

(at 20 mV/dB) is now close to 1 ms.

2. As the IF is lowered, the capacitor must be increased accord-

ingly if gain ripple is to be avoided. Thus, to achieve the

same ripple at 455 kHz requires the 1 nF capacitor to be in-

creased to 0.022

µF.

3. In AM applications, the AGC loop must not track the modu-

lation envelope. The objective should be that the gain should

not vary by more than the amount required to introduce, say,

1% THD distortion at the lowest modulation frequency, say,

300 Hz. Note that in AM applications it is the modulation

bandwidth that determines the required AGC filter capaci-

tor, not the IF.

4. In some applications, even slower AGC may be desired than

that required to prevent modulation tracking.

AD607 EVALUATION BOARD

The AD607 evaluation board (Figures 46 and 47) consists of an

AD607, ground plane, I/O connectors, and a 10.7 MHz band-

pass filter. The RF and LO ports are terminated in 50

Ω to

provide a broadband match to external signal generators to al-

low a choice of RF and LO input frequencies. The IF filter is at

10.7 MHz and has 330

Ω input and output terminations; the

board is laid out to allow the user to substitute other filters for

other IFs.

Figure 46. Evaluation Board

FDIN

COM1

PRUP

LOIP

RFLO

RFHI

GREF

MXOP

VMID

IFHI

VPS1

FLTR

IOUT

QOUT

VPS2

DMIP

IFOP

COM2

GAIN

IFLO

AD607

C12

0.1µF

R9

0

C5

1nF

C6

0.1µF

C8

0.1µF

RSSI

IF

Q

I

C1

0.1µF

C3 10nF

R1

1k

Ω

C2 0.1µF

C4

47pF

R2

316

Ω

C15

0.1µF

JUMPER

JUMPER

C16

1nF

R10

4.99k

Ω

R11

OPEN

C11

10nF

R8

51.1

Ω

C13 0

C14 0

R7

51.1

Ω

R6

51.1

Ω

C10

1nF

C9

1nF

R5

332

Ω

R3

332

Ω

R4

0

C7

1nF

VPOS

GND

FDIN

PRUP

LO

RF

R13

50k

Ω

R15

50k

Ω

VPOS

FDIN

R12

OPEN

VMID

C17

10nF

C18

SHORT

R14

51.1

Ω

FDIN

MOD FOR LARGE MAGNITUDE

AC COUPLED INPUT

AD607 EVALUATION BOARD

(AS RECEIVED)

R18

OPEN

R17

OPEN

VPOS

FDIN

R16

OPEN

VMID

C20

SHORT

C19

ANYTHING

R19

RSOURCE

FDIN

MOD FOR DC COUPLED INPUT