REV. B

AD7887

–8–

PERFORMANCE CURVES

Figure 2 shows a typical FFT plot for the AD7887 at 125 kHz

sample rate and 10 kHz input frequency.

–110

0

–10

–30

–50

–70

–90

4096 POINT FFT

SAMPLING

125kSPS

SNR = 71dB

Figure 2. Dynamic Performance

Figure 3 shows the SNR vs. Frequency for a 5 V supply with a

5 V external reference.

INPUT FREQUENCY – kHz

71.0

0.15

42.14

73.0

72.5

72.0

71.5

10.89

31.59

5V EXT REFERENCE

21.14

Figure 3. SNR vs. Input Frequency

Figure 4 shows the power supply rejection ratio versus fre-

quency for the part. The power supply rejection ratio is defined

as the ratio of the power in the ADC output at frequency f to

the power of a full-scale sine wave applied to the ADC of fre-

PSRR (dB) = 10 log (Pf/Pfs)

Pf = Power at frequency f in ADC output, Pfs = power at fre-

+5.5 V supply performances are shown.

INPUT FREQUENCY – kHz

–93

2.65

64.15

12.85

33.65

23.15

–91

–89

–87

–85

–83

–81

–79

–77

–75

43.85

54.35

Figure 4. PSRR vs. Frequency

CIRCUIT INFORMATION

The AD7887 is a fast, low power, 12-bit, single supply, single-

channel/dual-channel A/D converter. The part can be operated

from a +3 V (+2.7 V to +3.6 V) supply or from a +5 V (+4.75 V to

+5.25 V) supply. When operated from either a +5 V or +3 V

supply, the AD7887 is capable of throughput rates of 125 kSPS

when provided with a 2 MHz clock.

The AD7887 provides the user with an on-chip track/hold, A/D

converter, reference and serial interface housed in an 8-lead

package. The serial clock input accesses data from the part and

also provides the clock source for the successive approximation

A/D converter. The part can be configured for single-channel or

dual-channel operation. When configured as a single-channel

AD7887 is configured for two input channels, the input range is

If single-channel operation is required, the AD7887 can be

operated in a read-only mode by tying the DIN line permanently to

GND. For applications where the user wants to change the

mode of operation or wants to operate the AD7887 as a dual-

channel A/D converter, the DIN line can be used to clock data

into the part’s control register.

CONVERTER OPERATION

The AD7887 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. Figures 5

and 6 show simplified schematics of the ADC. Figure 5 shows

the ADC during its acquisition phase. SW2 is closed and SW1 is

in position A, the comparator is held in a balanced condition

and the sampling capacitor acquires the signal on AIN.

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

ACQUISITION

PHASE

SW1

A

SW2

AGND

B

AIN

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 5. ADC Acquisition Phase