REV. B

AD7887

–13–

SCLK

CS

DOUT

DIN

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1

1

16

PM1 = 1 AND PM0 = 1 TO KEEP

THE PART IN THIS MODE

1

16

THE PART POWERS UP

FROM STANDBY ON SCLK

FALLING EDGE AS PM1 = 1

AND PM0 = 1

THE PART ENTERS

STANDBY AT THE END OF

CONVERSION AS

PM1 = 1 AND PM0 = 1

4 LEADING ZEROS + CONVERSION RESULT

DATA IN

4 LEADING ZEROS + CONVERSION RESULT

DATA IN

Figure 16. Mode 4 Operation

SERIAL INTERFACE

Figure 17 shows the detailed timing diagrams for serial interfac-

ing to the AD7887. The serial clock provides the conversion

clock and also controls the transfer of information to and from

the AD7887 during conversion.

CS initiates the data transfer and conversion process. For some

modes, the falling edge of CS wakes up the part. In all cases, it

gates the serial clock to the AD7887 and puts the on-chip track/

hold into track mode. The input signal is sampled on the second

rising edge of the SCLK input after the falling edge of CS. Thus,

the first one and one-half clock cycles after the falling edge of

CS are when the acquisition of the input signal takes place. This

the falling edge of CS wakes up the part, the acquisition time

must allow for the wake-up time of 5

µs. The on-chip track/hold

goes from track mode to hold mode on the second rising edge of

SCLK and a conversion is also initiated on this edge. The con-

version process takes a further fourteen and one-half SCLK

cycles to complete. The rising edge of CS will put the bus back

into three-state. If CS is left low a new conversion will be initiated.

In dual-channel operation, the input channel that is sampled is

the one that was selected in the previous write to the Control

Register. Thus, in dual-channel operation the user must write

ahead the channel for conversion. In other words, the user must

write the channel address for the next conversion while the

present conversion is in progress.

Writing of information to the Control Register takes place on the

first eight rising edges of SCLK in a data transfer. The Control

Register is always written to when a data transfer takes place.

However, the AD7887 can be operated in a read-only mode by

tying DIN low, thereby loading all 0s to the Control Register

every time. When operating the AD7887 in write/read mode, the

user must be careful to always set up the correct information on

the DIN line when reading data from the part.

Sixteen serial clock cycles are required to perform the conversion

process and to access data from the AD7887. In applications

where the first serial clock edge, following CS going low, is a

falling edge, this edge clocks out the first leading zero. Thus, the

first rising clock edge on the SCLK clock has the first leading

zero provided. In applications where the first serial clock edge,

following CS going low, is a rising edge, the first leading zero

may not be set up in time for the processor to read it correctly.

However, subsequent bits are clocked out on the falling edge of

SCLK so that they are provided to the processor on the follow-

ing rising edge. Thus, the second leading zero is clocked out on

the falling edge subsequent to the first rising edge. The final bit

in the data transfer is valid on the sixteenth rising edge, having

being clocked out on the previous falling edge.

DONTC

ZERO

ZERO

REF

SIN/DUAL

CH

PM1

PM0

SCLK

15

6

15

DOUT

DIN

23

4

16

DB11

DB0

DB10

DB9

THREE-

STATE

4 LEADING ZEROS

CS

THREE-

STATE

Figure 17. Serial Interface Timing Diagram