REV. B

AD7887

–9–

When the ADC starts a conversion (see Figure 6), SW2 will

open and SW1 will move to Position B causing the comparator

to become unbalanced. The control logic and the charge redis-

tribution DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced the conversion is complete. The control logic generates

the ADC output code. Figure 7 shows the ADC transfer function.

CONVERSION

PHASE

REF IN/REF OUT/2

SAMPLING

CAPACITOR

COMPARATOR

CONTROL

LOGIC

SW1

A

SW2

AGND

B

CHARGE

REDISTRIBUTION

DAC

Figure 6. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7887 is straight binary. The de-

signed code transitions occur at successive integer LSB values

ideal transfer characteristic for the AD7887 is shown in Figure 7.

0V

ANALOG INPUT

111...000

011...111

0.5LSB

111...111

111...110

000...010

000...001

000...000

Figure 7. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 8 shows a typical connection diagram for the AD7887.

The GND pin is connected to the analog ground plane of the

16-bit word with four leading zeros followed by the MSB of the

12-bit result. For applications where power consumption is of

concern, the automatic power-down at the end of conversion

should be used to improve power performance. See Modes of

Operation section of the data sheet.

DOUT

DIN

SCLK

CS

AIN1

AIN2

GND

0.1 F

10 F

SUPPLY +2.7V

TO +5.25V

SERIAL

INTERFACE

AD7887

INPUT

C/ P

Figure 8. Typical Connection Diagram

Analog Input

Figure 9 shows an equivalent circuit of the analog input structure

of the AD7887. The two diodes D1 and D2 provide ESD pro-

tection for the analog inputs. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more

than 200 mV. This will cause these diodes to become forward

biased and start conducting current into the substrate. 20 mA is

the maximum current these diodes can conduct without causing

irreversible damage to the part. However, it is worth noting that

a small amount of current (1 mA) being conducted into the

substrate due to an overvoltage on an unselected channel can

cause inaccurate conversions on a selected channel. The capaci-

tor C1 in Figure 9 is typically about 4 pF and can primarily be

attributed to pin capacitance. The resistor R1 is a lumped

component made up of the on resistance of a multiplexer and a

switch. This resistor is typically about 100

Ω. The capacitor C2

is the ADC sampling capacitor and typically has a capacitance

of 20 pF.

Note: The analog input capacitance seen when in track mode is

typically 38 pF while in hold mode it is typically 4 pF.

D2

R1

C1

4pF

CONVERSION PHASE – SWITCH OPEN

TRACK PHASE – SWITCH CLOSED

D1

C2

20pF

Figure 9. Equivalent Analog Input Circuit

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC low-

pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal to noise ratio are critical,

the analog input should be driven from a low impedance source.

Large source impedances will significantly affect the ac perfor-

mance of the ADC. This may necessitate the use of an input

buffer amplifier. The choice of the op amp will be a function of

the particular application.

When no amplifier is used to drive the analog input the source

impedance should be limited to low values. The maximum

source impedance will depend on the amount of total harmonic

distortion (THD) that can be tolerated. The THD will increase