REV. B

AD7887

–12–

Mode 3 (PM1 = 1, PM0 = 0)

In this mode, the AD7887 automatically enters its full shutdown

mode at the end of every conversion. It is similar to Mode 1

except that the status of CS does not have any effect on the

power-down status of the AD7887.

Figure 15a shows the general diagram of the operation of the

AD7887 in this mode. On the first falling SCLK edge after CS

goes low, all on-chip circuitry starts to power up. It takes ap-

proximately, 5

µs for the AD7887 internal circuitry to be fully

powered up. As a result, a conversion (or sample-and-hold

acquisition) should not be initiated during this 5

µs. The input

signal is sampled on the second rising edge of SCLK following

the CS falling edge. The user should ensure that 5

µs elapses

between the first falling edge of SCLK and the second rising

edge of SCLK after the CS falling edge as shown in Figure 15a.

In microcontroller applications (or with a slow serial clock) this

is readily achievable by driving the CS input from one of the

port lines and ensuring that the serial data read (from the micro-

controller’s serial port) is not initiated for 5

µs. However, for

higher speed serial clocks it will not be possible to have a 5

µs

delay between powering up and the first rising edge of the SCLK.

Therefore, the user will need to write to the Control Register to

exit this mode and (by writing PM1 = 0 and PM0 = 1) put the

part into Mode 2. A second conversion will then need to be

initiated when the part is powered up to get a conversion result, as

shown in Figure 15b. The write operation that takes place in

conjunction with this second conversion can put the part back

into Mode 3 and the part will go into power-down mode when

the conversion sequence ends.

Mode 4 (PM1 = 1, PM0 = 1)

In this mode, the AD7887 automatically enters a standby (or

sleep) mode at the end of every conversion. In this standby

mode, all on-chip circuitry, apart from the on-chip reference, is

powered down. This mode is similar to Mode 3 but in this case,

the power-up time is much shorter as the on-chip reference

remains powered up at all times.

Figure 16 shows the general diagram of the operation of the

AD7887 in this mode. On the first falling SCLK edge after CS

goes low, the AD7887 comes out of standby. The AD7887

wake-up time is very short in this mode so it is possible to wake-

up the part and carry out a valid conversion in the same read/

write operation. The input signal is sampled on the second

rising edge of SCLK following the CS falling edge. At the end of

conversion (last rising edge of SCLK) the part automatically

enters its standby mode.

SCLK

CS

DOUT

DIN

THE PART POWERS UP FROM

SHUTDOWN ON SCLK FALLING EDGE AS

PM1 = 1 AND PM0 = 0

1

16

1

16

2

THE PART ENTERS

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1 AND PM0 = 0

CONTROL REGISTER DATA IS LOADED ON THE

FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0

PM1 = 1 AND PM0 = 0 TO KEEP THE

PART IN THIS MODE

DATA IN

DATA IN

4 LEADING ZEROS + CONVERSION RESULT

4 LEADING ZEROS + CONVERSION RESULT

Figure 15a. Mode 3 Operation

SCLK

CS

DOUT

DIN

1

16

8

1

16

8

1

16

8

PM1 = 0 AND PM0 = 1 TO PLACE

THE PART IN NORMAL MODE

PM1 = 1 AND PM0 = 0 TO PLACE

THE PART BACK IN MODE 3

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0

THE PART ENTERS

SHUTDOWN AT THE END

OF CONVERSION AS

PM1 = 1 AND PM0 = 0

THE PART REMAINS POWERED UP

AS PM1 = 0 AND PM0 = 1

THE PART BEGINS TO POWER

UP FROM SHUTDOWN

THE PART ENTERS

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1

AND PM0 = 0

4 LEADING ZEROS

+ CONVERSION RESULT

DATA IN

4 LEADING ZEROS

+ CONVERSION RESULT

DATA IN

4 LEADING ZEROS

+ CONVERSION RESULT

DATA IN

Figure 15b. Mode 3 Operation