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AD8151AST 数据表(PDF) 14 Page - Analog Devices

部件名 AD8151AST
功能描述  33 x 17, 3.2 Gb/s Digital Crosspoint Switch
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8151AST 数据表(HTML) 14 Page - Analog Devices

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AD8151
–14–
REV. 0
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
WE INPUT
tCSU
tUOT
tUOE
tWOT
tWHU
INPUT {DATA 1}
INPUT {DATA 1}
INPUT {DATA 2}
INPUT {DATA 0}
tCHU
tUW
tWOD
Figure 5. First Rank Write Cycle and Second Rank Update Cycle
Table V. First Rank Write Cycle and Second Rank Update Cycle
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCSU
Setup Time
Chip Select to Update
TA = 25
°C0
ns
tCHU
Hold Time
Chip Select from Update
VDD = 5 V
0
ns
tUOE
Output Enable Times
Update to Output Enable
VCC = 3.3 V
25
40
ns
tWOE*
Write Enable to Output Enable
25
40
ns
tUOT
Output Toggle Times
Update to Output Reprogram
25
30
ns
tWOT
Write Enable to Output Reprogram
25
30
ns
tUOD*
Output Disable Times
Update to Output Disabled
25
30
ns
tWOD
Write Enable to Output Disabled
25
30
ns
tWHU
Setup Time
Write Enable to Update
10
ns
tUW
Width of Update Pulse
15
ns
*Not Shown.
A[4:0]
INPUTS
tCSR
D[6:0]
OUTPUTS
tRDE
tAA
tRHA
CS INPUT
RE INPUT
ADDR 1
ADDR 2
DATA
{ADDR1}
DATA {ADDR2}
tCHR
tRDD
Figure 6. Second Rank Readback Cycle
Table VI. Second Rank Readback Cycle
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tCSR
Setup Time
Chip Select to Read Enable
TA = 25
°C0
ns
tCHR
Hold Time
Chip Select from Read Enable
VDD = 5 V
0
ns
tRHA
Address from Read Enable
VCC = 3.3 V
5
ns
tRDE
Enable Time
Data from Read Enable
10 k
Ω
15
ns
tAA
Access Time
Data from Address
20 pF on D[6:0]
15
ns
tRDD
Release Time
Data from Read Enable
Bus
15
30
ns



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