AD8151AST datasheet(21/36 Pages) AD

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AD8151

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external pin of the AD8151 projects into the package, and has a

bond wire connected to the chip inside. On-chip wiring then

connects to the collectors of the output transistors and to ESD

protection diodes.

Unlike some other high-speed digital components, the AD8151

does not have on-chip terminations. While this location would

be closer to the actual end of the transmission line for some

architectures, this concept can limit system design options. In

particular, it is not possible to bus more than two inputs or

outputs on the same transmission line and it is also not possible

to change the value of these terminations to use for different

impedance transmission lines. The AD8151, with the added

ability to disable its outputs, is much more versatile in these

types of architectures.

If the external traces are kept to a bare minimum, then the

output will present a mostly lumped capacitive load of about

2 pF. A single stub of 2 pF will not seriously adversely affect

signal integrity for most transmission lines, but the more of

these stubs, the more adverse their influence will be.

One way to mitigate this effect is to locally reduce the capacitance

of the main transmission line near the point of stub intersection.

Some practical means for doing this are to narrow the PC board

traces in the region of the stub and/or to remove some of the

ground plane(s) near this intersection. The effect of these tech-

niques will locally lower the capacitance of the main transmission

line at these points, while the added capacitance of the AD8151

outputs will “compensate” for this reduction in capacitance.

The overall intent is to create as uniform a transmission line as

possible.

In selecting the location of the termination resistors it is impor-

tant to keep in mind that, as their name implies, they should be

placed at either end of the line. There should be no or minimal

projection of the transmission line beyond the point where the

termination resistors connect to it.

EVALUATION BOARD

An evaluation board has been designed and is available to rapidly

test the main features of the AD8151. This board lets the user

analyze the analog performance of the AD8151 channels and

easily control the configuration of the board by a standard PC.

The board has limited numbers of differential input/output

pairs. Each differential pair of microstrip is connected to either

top-mount or side-launch SMA connectors. The top-mount

SMA connectors are drilled and stubbed for superior perfor-

mance. The FR4 type board contains a total of nine outputs (all

even numbered outputs) and 20 inputs (numbers 0, 2, 4, 6, 8,

10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is

important to note that the shells of the SMA connectors are

attached to VCC. This makes only ECL or negative level swings

possible during testing.

Power Supplies

The AD8151 is designed to work with standard ECL logic levels.

This means that VCC is at ground and VEE is at a negative supply.

The shells of the I/O SMA connectors are at VCC potential. Thus,

when operating in the standard ECL configuration, test equipment

can be directly connected to the board, as the test equipment

will have its connector “shells” at ground potential also.

Operating in PECL mode requires VCC to be at a positive volt-

age, while VEE is at ground. Since this would make the shells of

the I/O connectors at a positive voltage, it can cause problems

when directly connecting to test equipment. Some equipment,

such as battery-operated oscilloscopes, can be “floated” from

ground, but care should be taken with line-powered equipment

to avoid creating a dangerous situation. Refer to the manual of

the test equipment that is being used.

The voltage difference from VCC to VEE can range from 3 V to

5 V. Power savings can be realized by operating at a lower volt-

age without any compromise in performance.

A separate connection is provided for VTT, the termination

potential of the outputs. This can be at a voltage as high as VCC,

but power savings can be realized if VTT is at a voltage that is

somewhat lower. Please consult elsewhere in the data sheet for

the specification for the limits of the VTT supply.

As a practical matter, current on the evaluation board will flow

from the VTT supply, through the termination resistors, into the

multiple outputs of the AD8151, and on to the VEE supply. When

running in ECL mode, VTT will want to be at a negative supply.

Most power supplies will not allow their ground connection to

VCC and then the negative supply to VTT. This will require them

to source current from their negative supply, which wants to

flow to the more-negative VEE. This current will not then return

to the ground terminal of the VTT supply. Thus, VTT should be

referenced to VEE when running in ECL mode or a true bipolar

supply should be used.

The digital supply is provided to the AD8151 by the VDD and

VSS pins. VSS should always be at ground potential to make it

compatible with standard CMOS or TTL logic. VDD can range

from 3 V to 5 V, and should be matched to the supply voltage of

the logic used to control the AD8151. However, since PCs use

5 V logic on their parallel port, VDD should be at 5 V when using a

PC to program the AD8151.

Bypassing

Most of the board’s bypass capacitors are opposite the DUT on

the solder side, connected between VCC and VEE. This is where

they will be most effective. These capacitors are 0.01

µF ceramic

chip capacitors for low inductance. There are additional higher

value capacitors elsewhere on the board for bypassing at lower

frequencies. The location of these is not as critical.

Input and Output Considerations

Each input contains a 100

Ω differential termination. Although

the differential termination eases board layout due to its compact

nature, it can cause problems with the driving generator. A typical

pulse or pattern generator wants to see 50

Ω to ground (or to

–2 V in some cases). High speed probing of the input showed if

this type of termination is not present then input amplitudes could

be slightly off. Even more affected can be the dc input levels.

Depending on the generator used, these levels can be off as much

as 800 mV in either direction. A correction for this problem is to

attach a 6 dB attenuator to each P and N input. Because the

AD8151 has a large common-mode voltage range on its input

stage, it will not be significantly affected by dc level errors.

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