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AD9430/PCB-CMOS 数据表(PDF) 6 Page - Analog Devices |
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AD9430/PCB-CMOS 数据表(HTML) 6 Page - Analog Devices |
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6 / 20 page ![]() PRELIMINARY TECHNICAL DATA AD9430 -6- 4/01/2002 REV. PrG ABSOLUTE MAXIMUM RATINGS AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . .. . .. . . –0.5 V to AVDD + 0.5 V Digital Inputs . . .. . . . . . . . .. . . .. –0.5 V to DRVDD + 0.5 V REFIN Inputs . . . . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . ... . . . . . –55C to +125C Storage Temperature . . . . . . . . . . . . . ... . . . . –65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C θ JA 2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W NOTES EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical θ JA = 32C/W (heat slug not soldered), Typical θ JA = 25C/W (heat slug soldered), for multilayer board in still air. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality . ORDERING GUIDE Model Temperature Range Package Option AD9430BSV-170 –40°C to +85°C TQFP–100 AD9430/PCB-CMOS +25°C Evaluatio n Board (CMOS Mode) Table 1. AD9430 Output Select Coding S1 (Data Format Select) 1 S2 (LVDS/CMOS Output Mode Select ) S4 (Select Interleaved or Parallel Mode) 2 S5 (Full Scale Adjust) Mode 1 X X X 2’s Complement 0 X X X Offset Binary X 0 1 X Dual Mode CMOS Interleaved X 0 0 X Dual Mode CMOS Parallel X 1 X X LVDS Mode X X X 1 Full Scale -> .766 Vpp differential 1.533 Vpp Single- Ended X X X 0 Full Scale -> 1.533 Vpp differential Notes: 1 X = Don’t Care S1-S5 all have 30K resistive pulldowns on chip 2In interleaved mode output data on port A is offset from output data changes on port B by ½ output clock cycle. Interleaved mode Parallel Mode |
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