AD9430SLASHPCB-CMOS datasheet(2/20 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9430

-2-

4/01/2002 REV. PrG

DC SPECIFICATIONS

(AV

DD= DrVDD = 3.3V; TMIN = -40°C, TMAX = +85°C, Fin = -0.5dBFS, 1.235V External

reference, LVDS Output Mode

)

Parameter

Temp

Test

Level

AD9430BSV-170

Min

Typ

Max

Units

RESOLUTION

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

Full

°C

Guaranteed

tbd

+/- .3

+/- .5

% FS

LSB

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

tbd

ppm/

°C

ppm/

°C

POWER SUPPLY REJECTION

Full

± tbd

mV/V

REFERENCE OUT (VREF)

Full

1.235

ANALOG INPUTS (AIN, AIN )

Input Voltage Range (AIN– AIN )

Input Common Mode Voltage

Input Resistance

Input Capacitance

Full

± .768

2.8

Ω

POWER SUPPLY

Supply Voltages

DrVDD

Supply Current

I ANALOG (AVDD= 3.3V)

I DIGITAL (DrVDD = 3.3V)

Full

3.0

3.3

3.6

3.0

3.3

3.6

335

POWER CONSUMPTION

Full

1.29

NOTES

Nominal Differential Full Scale = .766 V * 2 = 1.53 Vp-p differential for S5 = 0; Nominal Differential Full Scale = .766 Vp-p differential for S5 = 1 (see Fig. X)

2 IAVDD and IDrVDD are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance

Characteristics and Applications section for IDrVDD. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode

DIGITAL SPECIFICATIONS (

DD= 3.3V, DrVDD = 3.3V; TMIN = -40°

°C, T

MAX = +85°

°C)

Parameter (Conditions)

Temp

Test

Level

AD9430BSV-170

Min

Typ

Max

Units

ENCODE AND DATA SYNC

INPUTS (ENC, ENC , DS, DS/ )

Differential Input Voltage

Encode Common Mode Voltage

Input Resistance

Input Capacitance

LOGIC INPUTS ( S1,S2,S4,S5 )

Logic ‘1’ Voltage

Logic ‘0’ Voltage

Input Resistance

Input Capacitance

Full

0.2

1.5

5.5

2.0

Ω

LOGIC OUTPUTS (Demux Mode)

Logic “1” Voltage

Logic “0” Voltage

LOGIC OUTPUTS (LVDS Mode)

2,3

VOD

Differential Output Voltage

VOS

Output Offset Voltage

Output Coding

Full

DrVDD-0.05

0.05

247

454

1.125

1.375

Two’s Comp or Binary

NOTES

1All AC specifications tested by driving ENCODE and ENCODE differentially

| ENCODE - ENCODE

| > 200mV

2Digital Output Logic Levels:

DrVDD= 3.3V, CLOAD = 5pF.

3 LVDS Rl=100 ohms, LVDS Output Swing Set Resistor = 3.7K

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